expression has 2 elements, but must have 4 elements

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I think you are making some confusion with types.

Infact:

A and B are defined as an array of 2 unsigned elements

OUTPUT is defined as an array of 4 unsigned elements

OUTPUT <= A sll C shifts left A by C (=B) bits

I'm not a vhdl expert but I think than sll must always operate on a bit vector (error1: here you have an unsigned int vector) ; then you assign the result to a different size array (error2: A size 2, OUTPUT size 4)

Probably you are confusing array dimensions with ranges.

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sll is defined for bit_vector, unsigned and signed.

Another way to may it work would have been:

output <= ("00" & A) sll C;