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Altera_Forum
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15 years ago

expression has 2 elements, but must have 4 elements

Hey guys, This is trashing my brain, please help. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; EN...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think you are making some confusion with types.

Infact:

A and B are defined as an array of 2 unsigned elements

OUTPUT is defined as an array of 4 unsigned elements

OUTPUT <= A sll C shifts left A by C (=B) bits

I'm not a vhdl expert but I think than sll must always operate on a bit vector (error1: here you have an unsigned int vector) ; then you assign the result to a different size array (error2: A size 2, OUTPUT size 4)

Probably you are confusing array dimensions with ranges.