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Altera_Forum's avatar
Altera_Forum
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15 years ago

error:Subprogram Body cannot contain Wait Statement

Hello everyone.

I'm studying VHDL in university. I got an error when tried to write description of d-flip-flop with using procedure in QuartusII.

"Error (10532): Subprogram Body cannot contain Wait Statement"

I used help and found out two things:

1. VHDL is completely integrated into the Quartus II system.

2. Action to correct error - Remove the Wait Statement from the Subprogram Body, or place the Wait Statement outside the Subprogram Body. (there is link on Sections 2.2 and 8.1 of the IEEE Std 1076-1993)

But in section 8.1 of IEEE Std is written "The wait statement causes the suspension of a process statement or a procedure." So I think this error conflicts with VHDL Standart. Can anyone comment this?

P.S. Sorry for my english, I don't know it very well :D.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Quartus does not support full set of vhdl but only the synthesis subset. These issues are not static facts but tool-related. So take it easy.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    But I thought this should belong synthesis subset, because Quartus can synthesise functions into a logic.

    I wanna it works ... :cry:

    I just wanted to use it like in AHDL (something like a=DFF(d,clk,,)).

    Why don't Altera do some mechanism of using this construction for VHDL?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The standard may to do a flip flop in synthesizable VHDL is to create a process and put your code in a if rising_edge(clk) block. The wait statements in processes are usually not synthesizable.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks to all. I found answer on my question.

    It was just an experiment (unfortunately unsuccessful).