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Altera_Forum
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15 years ago

error:Subprogram Body cannot contain Wait Statement

Hello everyone. I'm studying VHDL in university. I got an error when tried to write description of d-flip-flop with using procedure in QuartusII. "Error (10532): Subprogram Body cannot contai...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The standard may to do a flip flop in synthesizable VHDL is to create a process and put your code in a if rising_edge(clk) block. The wait statements in processes are usually not synthesizable.