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Altera_Forum's avatar
Altera_Forum
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11 years ago

Error with LMP counter component..

Hi all,

I have a design where I use the LPM_counter as a component "offline".

But, I get an error, which to me does not give any meaning... (See below text).

Does anyone have an idea of what I am doing wrong here...

Best Regards:

Martin C.

tools:

I am using Quartus 2 ver. 14.02.209. 64-bit.

Top_level vhd file is attached.

offline vhd file is attached.

The error points to line 236 of file: lpm_counter.tdf (also attached_changed extension for upload).

below is complete message read out from analysis:

--- Quote Start ---

Info: *******************************************************************

Info: Running Quartus II 64-Bit Analysis & Synthesis

Info: Version 14.0.2 Build 209 09/17/2014 SJ Web Edition

Info: Processing started: Tue Nov 04 14:11:56 2014

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DMB512 -c DMB512

Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

Info (12021): Found 2 design units, including 1 entities, in source file fsm.vhd

Info (12022): Found design unit 1: FSM-Behavioral

Info (12023): Found entity 1: FSM

Info (12021): Found 2 design units, including 1 entities, in source file top_level.vhd

Info (12022): Found design unit 1: Top_level-Top_level_architecture

Info (12023): Found entity 1: Top_level

Info (12021): Found 1 design units, including 1 entities, in source file dmb512.bdf

Info (12023): Found entity 1: DMB512

Info (12021): Found 2 design units, including 1 entities, in source file filter.vhd

Info (12022): Found design unit 1: Filter-Behavioral

Info (12023): Found entity 1: Filter

Info (12021): Found 2 design units, including 1 entities, in source file clockcounter.vhd

Info (12022): Found design unit 1: ClockCounter-Behavioral

Info (12023): Found entity 1: ClockCounter

Info (12021): Found 2 design units, including 1 entities, in source file tb_clockcounter.vhd

Info (12022): Found design unit 1: tb_ClockCounter-behavior

Info (12023): Found entity 1: tb_ClockCounter

Info (12021): Found 2 design units, including 1 entities, in source file send_p.vhd

Info (12022): Found design unit 1: send_p-Behavioral

Info (12023): Found entity 1: send_p

Info (12021): Found 2 design units, including 1 entities, in source file offline.vhd

Info (12022): Found design unit 1: offline-SYN

Info (12023): Found entity 1: offline

Info (12127): Elaborating entity "DMB512" for the top level hierarchy

Info (12128): Elaborating entity "Top_level" for hierarchy "Top_level:inst"

Info (12128): Elaborating entity "ClockCounter" for hierarchy "Top_level:inst|ClockCounter:Clock4800"

Info (12128): Elaborating entity "ClockCounter" for hierarchy "Top_level:inst|ClockCounter:Clock1200"

Info (12128): Elaborating entity "ClockCounter" for hierarchy "Top_level:inst|ClockCounter:LED_dimmer"

Info (12128): Elaborating entity "Filter" for hierarchy "Top_level:inst|Filter:P1Filter"

Info (12128): Elaborating entity "FSM" for hierarchy "Top_level:inst|FSM:STATEMACHINE"

Info (12128): Elaborating entity "offline" for hierarchy "Top_level:inst|offline:offline_comp1"

Error (287127): Text Design File syntax error: Text Design File contains '(' where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected

Error (287127): Text Design File syntax error: Text Design File contains IF where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected

Error (287127): Text Design File syntax error: Text Design File contains a symbolic name where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected

Error (287127): Text Design File syntax error: Text Design File contains IF where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected

Error (287127): Text Design File syntax error: Text Design File contains ELSE where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected

Error (287127): Text Design File syntax error: Text Design File contains ELSE where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS, PARAMETERS, SUBDESIGN, or TITLE was expected

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings

Error: Peak virtual memory: 548 megabytes

Error: Processing ended: Tue Nov 04 14:11:59 2014

Error: Elapsed time: 00:00:03

Error: Total CPU time (on all processors): 00:00:02

--- Quote End ---

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Doesn't your first line need "is" at the end of it?

    component offline is
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi ghogerheiden,

    The syntax does not require "is" in declaration of the component.

    (no difference with/without).
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Most likely a trivial syntax error. But don't expect meaningful answers without posting a complete source file, or at least the source text up to the first error.

    P.S.: I just noticed that the error message refers to AHDL code, e.g. lpm_counter.tdf or some of it's imported files. In this case, the problem might be an illegal or unexpected lpm_counter configuration. Please check which file and code line is marked in the error message. An post the lpm_counter instance files, e.g. offline.vhd.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Is there any reason why you have an ahdl lpm counter when you have a vhdl design?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Is there any reason why you have an ahdl lpm counter when you have a vhdl design?

    --- Quote End ---

    I use the LPM counter component which is part of Quartus II sw, megafunction.

    Easy/quick way to get a counter, thats why :-)

    Br Martin.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Yes - but when you generate the counter - you have the choice of which language to generate it in. Why did you chose AHDL, rather than VHDL?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Yes - but when you generate the counter - you have the choice of which language to generate it in. Why did you chose AHDL, rather than VHDL?

    --- Quote End ---

    I have not specifically chosen it to be an AHDL LPM component. (can't see how to chose between the two).

    Project settings are set to use VHDL IP settings.

    Project settings -> IP settings -> "IP generation HDL preference:" VHDL.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You specify the language for the output entity when you generate the core. Not in the project settings.

    The LPM_counter.tdf.txt you posted doesnt seem to be a megawizard file? where did you get it from? it looks like library code to me - that shouldnt be included in your project.

    From the looks of it, offline is the component you generated.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    You specify the language for the output entity when you generate the core. Not in the project settings.

    The LPM_counter.tdf.txt you posted doesnt seem to be a megawizard file? where did you get it from? it looks like library code to me - that shouldnt be included in your project.

    From the looks of it, offline is the component you generated.

    --- Quote End ---

    The file: LPM_counter.tdf.txt is not "included" in my project by me, it is where I am pointed, if I double click the error in the message window: 

    Error (287127): Text Design File syntax error: Text Design File contains  '(' where ASSERT, CONSTANT, DEFINE, DESIGN, FUNCTION, OPTIONS,  PARAMETERS, SUBDESIGN, or TITLE was expected

    So yes, this looks like a library file, but why do I get an error which points here? (Could there be a fault in the implementation of the LPM counter?).