Error: top level design entity " " is undefined

I had the same problem when I first started a while back. The solution I found that allowed Quartus II to compile my Verilog files was:

1)File | New | Block Diagram/Schematic File with the same name as Project

2)Click on the HDL source files (*.v etc) (it must be the active window)

3)File | Create/Update | Create Symbol File for Current File

4)Double click on the ProjectName.BDF file you created in Step 1 and insert your new Symbols from you made in step 3

5)Double click on the ProjectName.BDF file you created in Step 1 and insert pin assignments (Inputs, Outputs, etc)

Now Quartus II allowed my verilog modules to compile.

Cheers