error in my code

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i have error in control port map line.........

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Is this a guessing game? Any reason why you didn't post the exact error message?

Apparently you got confused with your port signals. It's a likely thing when using positional association in port maps.

Hi, I advise you to make 1 file per 1 entity. This is more maintainable like this. And you will debug easier.

Please Copy and paste your entire error message. Which entiy, which line.

thanks for your proposition but you won't work ;-).

As fvm said (http://www.alteraforum.com/forum/showthread.php?t=40296&p=166311#post166311) Avoid using positional port mapping, use named port mapping

the error msg i paste here plz read it........i already make all files expect control unit and these all files are working in altera de2-115 kit..... sir if u have quartus II software then you can see rtl view of code by removing the error line only.......thanks for reply

[# Reading C:/altera/11.1/modelsim_ase/tcl/vsim/pref.tcl

#

vcom -reportprogress 300 -work work C:/Users/vijay/Desktop/work/shankar.vhd

# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package std_logic_arith

# -- Compiling package cpu_lib

# -- Loading package cpu_lib

# -- Compiling entity cpu

# -- Compiling architecture rtl of cpu

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(112): Signal "shiftsel" is type work.cpu_lib.t_shift; expecting type ieee.std_logic_1164.STD_LOGIC.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(112): Signal "alusel" is type work.cpu_lib.t_alu; expecting type ieee.std_logic_1164.STD_LOGIC.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "regsel" is type work.cpu_lib.t_reg; expecting type ieee.std_logic_1164.STD_LOGIC.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "regRd" is type ieee.std_logic_1164.STD_LOGIC; expecting type work.cpu_lib.t_shift.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "regWr" is type ieee.std_logic_1164.STD_LOGIC; expecting type work.cpu_lib.t_alu.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "instrWr" is type ieee.std_logic_1164.STD_LOGIC; expecting type work.cpu_lib.t_reg.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(117): VHDL Compiler exiting]

In your entity cpu architecture rtl, at line "con: control..." do named port mapping (already said)

There is a mismatch in positions of ports of your "control" component.