error in my code

the error msg i paste here plz read it........i already make all files expect control unit and these all files are working in altera de2-115 kit..... sir if u have quartus II software then you can see rtl view of code by removing the error line only.......thanks for reply

[# Reading C:/altera/11.1/modelsim_ase/tcl/vsim/pref.tcl

#

vcom -reportprogress 300 -work work C:/Users/vijay/Desktop/work/shankar.vhd

# Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package std_logic_arith

# -- Compiling package cpu_lib

# -- Loading package cpu_lib

# -- Compiling entity cpu

# -- Compiling architecture rtl of cpu

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(112): Signal "shiftsel" is type work.cpu_lib.t_shift; expecting type ieee.std_logic_1164.STD_LOGIC.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(112): Signal "alusel" is type work.cpu_lib.t_alu; expecting type ieee.std_logic_1164.STD_LOGIC.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "regsel" is type work.cpu_lib.t_reg; expecting type ieee.std_logic_1164.STD_LOGIC.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "regRd" is type ieee.std_logic_1164.STD_LOGIC; expecting type work.cpu_lib.t_shift.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "regWr" is type ieee.std_logic_1164.STD_LOGIC; expecting type work.cpu_lib.t_alu.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(113): Signal "instrWr" is type ieee.std_logic_1164.STD_LOGIC; expecting type work.cpu_lib.t_reg.

# ** Error: C:/Users/vijay/Desktop/work/shankar.vhd(117): VHDL Compiler exiting]