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Altera_Forum
Honored Contributor
13 years agoIn your entity cpu architecture rtl, at line "con: control..." do named port mapping (already said)
There is a mismatch in positions of ports of your "control" component.In your entity cpu architecture rtl, at line "con: control..." do named port mapping (already said)
There is a mismatch in positions of ports of your "control" component.