Error during CPLD gate-level sim

I am running gate-level sim of a design, written in Verilog for a MAX3000A CPLD and I am getting errors. Does anyone know what is going on? What issue is the error indicating? Attaching the ModelSim transcript.

Thanks,

Tony

ModelSim transcript:

# Loading instances from spisram_v.sdo

# Loading timing data from spisram_v.sdo

# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.

# Time: 0 ps Iteration: 0 Region: /spisram_tb File: Z:/sram_clpd/altera/spisram_tb.v

# WARNING: No extended dataflow license exists

#

# add wave *

# view structure

# .main_pane.structure.interior.cs.body.struct

# view signals

# .main_pane.objects.interior.cs.body.tree

# run -all

# 0 << Starting the Simulation >>

# 0 addr=0000000000000000000, data=xxxxxxxx, ctrl=01, sclk=0, ss=1, mosi=0, miso=x

# 1 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=1, mosi=0, miso=z

# 20 << Single Write Test >>

# 20 << Slave Select >>

# 21 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=0, miso=z

# 22 << Driving byte: 07 >>

# 23 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=0, miso=z

# 25 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=0, miso=z

# 27 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=0, miso=z

# 29 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=0, miso=z

# 31 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=0, miso=z

# 33 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=0, miso=z

# 35 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=0, miso=z

# 37 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=0, miso=z

# 39 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=0, miso=z

# 41 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=0, miso=z

# 42 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=1, miso=z

# 43 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=1, miso=z

# 45 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=1, miso=z

# ** Error: C:/altera/11.0/modelsim_ase/win32aloem/../altera/verilog/src/max_atoms.v(2128): $setup( datain:44500 ps, posedge pclk[0] &&& reset:45200 ps, 1300 ps );

# Time: 45200 ps Iteration: 2 Instance: /spisram_tb/U1/\data0[5] /preg

# 47 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=1, miso=z

# 49 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=1, miso=z

# 51 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=1, ss=0, mosi=1, miso=z

# 53 addr=0000000000000000000, data=zzzzzzzz, ctrl=01, sclk=0, ss=0, mosi=1, miso=z