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Altera_Forum
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14 years ago

Error during CPLD gate-level sim

I am running gate-level sim of a design, written in Verilog for a MAX3000A CPLD and I am getting errors. Does anyone know what is going on? What issue is the error indicating? Attaching the ModelSim ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

So it's apparently a regular timing violation assertion generated by the Altera libraries.

In my opinion, the message text is lacking some information.