Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Error during CPLD gate-level sim

I am running gate-level sim of a design, written in Verilog for a MAX3000A CPLD and I am getting errors. Does anyone know what is going on? What issue is the error indicating? Attaching the ModelSim ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Looks like an "unknown" error, because the error number and description text according to the specified ModelSim message format are both missing.

Unless it's a known issue (you should check): report to Altera support.