Error during compilation when using 'Process'

Instantiating components as modules in your design is not done inside of a process.

Also, and this is purely personal, using positional notation for the signal declarations in your module instantiations is a monstrously evil thing that should be avoided like the plague.

BR

--- Quote Start ---

Instantiating components as modules in your design is not done inside of a process.

--- Quote End ---

How should I instantiate components?

--- Quote Start ---

Also, and this is purely personal, using positional notation for the signal declarations in your module instantiations is a monstrously evil thing that should be avoided like the plague.

--- Quote End ---

Sorry., I don't quite understand what you mean.. I'm only a few weeks into the world of VHDL so I am still not very familiar with the do's, don'ts and how to's of VHDL..

Can you please explain more or maybe show some sample coding of how i should do it..?

Thanks..

I have re-written your code snippet to try to show you what I mean.

I have not checked it so please forgive any typos.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

Entity Adder4 is

port( C : in std_logic;

X, Y, clock : in std_logic_vector (1 downto 0);

R : out std_logic_vector (2 downto 0));

end Adder4;

Architecture Version1 of Adder4 is

signal Carry : std_logic;

component FullAdd3_B

port ( A, B, Cin, clk : in std_logic;

Sum, Cout : out std_logic);

end component;

begin

---

--- Instantiating modules is not done inside of a process

--- All I did was strip away the process statements

--- around your 2 instantiations of component FullAdd3_B

---

--- in the below example the signals in the

--- top level design are associated with

--- the signals in the component through

--- named association or explicit association

--- not by position

--- in this case the position is the same as

--- your component declaration, but it does

--- not have to be

UO1: FullAdd3_B PORT MAP (A => X(0),

B => Y(0),

Cin => C,

clk => clock(0),

Sum => R(0),

Cout => Carry);

--- in the instantiation below

--- which I have left as you had it

--- you are creating the association

--- between signals by way of the position

--- of the signals in the declaration

---

UO2: FullAdd3_B PORT MAP (X(1), Y(1), Carry, clock(1), R(2), R(1));

--- both methods are allowed

--- I just like the former as it

--- keeps me from stepping on my

--- own toes which I do enough

--- without even trying

end Version1;

I understand now.. Thanks..

Yeah, I prefer your way of using instantiation..

by the way, instead of instantiating like this

             UO1:     FullAdd3_B PORT MAP (A => X(0), 
                                                          B => Y(0),
                                                          Cin => C,
                                                          clk => clock(0),
                                                           Sum => R(0),
                                                           Cout => Carry);

If I accidentally reverse the sequence, for example as below

             UO1:     FullAdd3_B PORT MAP (A => X(0), 
                                                            Sum => R(0),
                                                           clk => clock(0),                                                            
Cin => C,
B => Y(0),
Cout => Carry);

will it still work..?

By the way, just to confirm.. Is "A <= B" in VHDL is same as "B => A"..? I've only used "<=" before.

You should have some minimum literature at hand, that shows the VHDL syntax. You can learn it e. g. from VHDL templates in Quartus editor. But I think, you may consult a detailed textbook.

Apart from better readability, one adavantage of named notation for component instantiation is, that the argument order can be changed. For this reason, both variants are equivalent.

The '=>' operator meaning is completely different from '<='. It's used for named notation in component instantiation and aggregates or for selection in case statements. See my first remark.