Error during compilation when using 'Process'

I understand now.. Thanks..

Yeah, I prefer your way of using instantiation..

by the way, instead of instantiating like this

             UO1:     FullAdd3_B PORT MAP (A => X(0), 
                                                          B => Y(0),
                                                          Cin => C,
                                                          clk => clock(0),
                                                           Sum => R(0),
                                                           Cout => Carry);

If I accidentally reverse the sequence, for example as below

             UO1:     FullAdd3_B PORT MAP (A => X(0), 
                                                            Sum => R(0),
                                                           clk => clock(0),                                                            
Cin => C,
B => Y(0),
Cout => Carry);

will it still work..?

By the way, just to confirm.. Is "A <= B" in VHDL is same as "B => A"..? I've only used "<=" before.