Error during compilation when using 'Process'

You should have some minimum literature at hand, that shows the VHDL syntax. You can learn it e. g. from VHDL templates in Quartus editor. But I think, you may consult a detailed textbook.

Apart from better readability, one adavantage of named notation for component instantiation is, that the argument order can be changed. For this reason, both variants are equivalent.

The '=>' operator meaning is completely different from '<='. It's used for named notation in component instantiation and aggregates or for selection in case statements. See my first remark.