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Instantiating components as modules in your design is not done inside of a process.
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How should I instantiate components?
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Also, and this is purely personal, using positional notation for the signal declarations in your module instantiations is a monstrously evil thing that should be avoided like the plague.
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Sorry., I don't quite understand what you mean.. I'm only a few weeks into the world of VHDL so I am still not very familiar with the do's, don'ts and how to's of VHDL..
Can you please explain more or maybe show some sample coding of how i should do it..?
Thanks..
Honored Contributor
