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Altera_Forum's avatar
Altera_Forum
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8 years ago

error: Channel support is not enabled

Hi,I compiled project PipeCNN on the github with Intel OpenCL SDK for FPGA 17.1 and get the following error

In file included from /home/wangjf/PipeCNN/project/__all_sources.cl:2:

PipeCNN/project/device/conv_pipe.cl:75:24: error: Channel support is not enabled

channel channel_vec data_ch attribute((depth(0)));

Anyone got an idea? Thanks in advance!!:-P

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I see that you have already opened an issue on Github about this; I recommend waiting for a response from the owner of the repository. My guess is that since the channel extension and functions have been renamed from Altera to Intel in Quartis v17.0 and above, while that project uses the old names, you are running into this issue.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    I see that you have already opened an issue on Github about this; I recommend waiting for a response from the owner of the repository. My guess is that since the channel extension and functions have been renamed from Altera to Intel in Quartis v17.0 and above, while that project uses the old names, you are running into this issue.

    --- Quote End ---

    BTW，I am trying to compile it with VERSION 16.1,however,it points out me that I must have a valid license.So,I can do nothing.:D

    Thanks a lot.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I changed OPENCL_EXTENSION in the Makefile to OPEN EXTENSION and it can solve the above problem.

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I had the same problem as you. Tried your method and still not working. Can you share how you finally worked it out? Thanks!

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi，can you tell me the details of your problems? Thanks.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I add both of these, and it can work.

    # pragma OPENCL_EXTENSION cl_altera_channels : enable

    # pragma OPENCL EXTENSION cl_intel_channels : enable
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    I add both of these, and it can work.

    # pragma OPENCL_EXTENSION cl_altera_channels : enable

    # pragma OPENCL EXTENSION cl_intel_channels : enable

    --- Quote End ---

    The first line can be deleted.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Hi，can you tell me the details of your problems? Thanks.

    --- Quote End ---

    Finally it worked out using# pragma OPENCL EXTENSION cl_intel_channels : enable

    In your original post it was# pragma OPEN EXTENSION cl_intel_channels : enable so it didn't work. Anyway thx!

    After successfully compiling the conv.aocx file with hw setting (which took hours), running it seems taking forever.. I'm wondering how long does it take you to run it on the FPGA device?