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danield17's avatar
danield17
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10 months ago

Error 23098 when compiling Agilex5 GTS PCIe

I tried to create a design with PCIe GTS IP core and SSGDMA on Agilex5 but I got the following error: One or more blocks are configured incorrectly and will not have the desired functionality. -...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
10 months ago

Hi,

I wish to follow up with you about this forum case.

Do you have any further questions on this matter ? Else do I have your permission to close this IPS ticket ?


Regards,

Wincent_Altera


danield17's avatar
danield17
Icon for New Contributor rankNew Contributor
10 months ago
Hi Wincent,

I appreciate the effort, but the solution isn’t entirely clear to me.

From what I’ve found so far, these errors seem to stem from IP core configurations and connections—possibly even missing ones—that the Fitter doesn’t accept. I still don’t fully understand why the specific errors I encountered were problematic, but after a few changes to the IP configurations, I managed to get rid of them.

For anyone searching for solutions to the specific errors mentioned above:

pf0_pci_type0_bar2_enabled and pf0_pci_type0_bar2_mask_31_1 error – I was able to resolve this by enabling BAR2.

vcc_hssi_level error – I cleared this one by changing the IP configuration from Gen 4 to Gen 3.


I really wish Intel would provide some documentation or clearer error messages to help users better understand the source and meaning of these issues.

Regards,
danield17
  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    10 months ago

    Hi Daniel,

    Is it possible to share your design .qar file here ?
    It will give me more visibility to the problem facing by you in order to provide more accurate answer towards the issue.

    Meanwhile,
    I really wish Intel would provide some documentation or clearer error messages to help users better understand the source and meaning of these issues.
    >> meaning of the error is due to an invalid combination of reference clock frequency and operating bit rate. (as mentioned in the earlier reply)

    I am using Quartus v24.3.
    I have currently selected PCIe gen4 x4 with 256-bit interface and a reference clock of 350MHz.
    >> did you try to recreate the project from empty ? or just perform IP upgrade ?
    >> I have experience the same issue as yours, by recreate the project in latest version of Quartus it does not appear anymore, this is happen due to Quartus IP improvement and prevent the invalid combination which causing the conflict.

    Regards,
    Wincent_Altera

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      10 months ago

      Hi Daniel,

      Any update from my previous reply ? especially on the .qar file.

      Regards,

      Wincent_Altera

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    10 months ago

    Hi Daniel,

    Sorry , I miss this message, glad that you are able to resolve the problem.
    Will submit an internal ticket to include this in next version of document (subject to change)
    Thanks for sharing with me how you workaround this.


    Regards,
    Wincent_Altera