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JHill1's avatar
JHill1
Icon for Occasional Contributor rankOccasional Contributor
17 days ago

Error (19021): The same file name "clock_in_0" is used for different IP files

 

Hello All!

Im curious how one fixes a hierarchical QSYS system related quartus compile error like the following given that the name "clock_in_0" was not chosen by the designer, but instead by platform designer, and is not something we can change in the Platform Designer GUI?

Is it necessary to hand edit the IP or QSYS/IP XML giberish files to fix such issues?

Given no other options that is probably what I will beforced to try next.

Thanks!

(/ade/fpga/altera/pro_22.4/quartus/sopc_builder/bin/qsys-generate ../../../top/ioc/fcm2_ioc.qsys --search-path="../../../pins, ../../../top, ../../../top/ioc, .., $" --family="Arria 10" --part=10AX066K4F40E3SG --synthesis=VHDL --clear-output-directory --jvm-max-heap-size=64g --quartus-project=fcm2 --rev=fcm2_adc || echo "cmd-fail-status" $?) |& perl ../../../../../../../build-sys/filter_quartus.pl   qsysgen    fcm2_ioc_qsys_gen_failed.log 

Ignoring env var, _JAVA_OPTIONS="-Xmx64g"
Please use env var, QSYS_EDIT_JVM_ARGS, to apply your JVM arguments to Qsys Pro
***************************************************************
Quartus is a registered trademark of Intel Corporation in the
US and other countries.  Portions of the Quartus Prime software
code, and other portions of the code included in this download
or on this DVD, are licensed to Intel Corporation and are the
copyrighted property of third parties. For license details,
refer to the End User License Agreement at
http://fpgasoftware.intel.com/eula.
***************************************************************

mv fcm2_ioc_qsys_gen_failed.log fcm2_ioc_qsys_gen.log
(/ade/fpga/altera/pro_22.4/quartus/bin/quartus_sh --no_banner --flow compile fcm2 -c fcm2_adc || echo "cmd-fail-status" $?) |& perl ../../../../../../../build-sys/filter_quartus.pl   quartus    fcm2.compile.log 
Error (19021): The same file name "clock_in_0" is used for different IP files. The same name cannot be used for more than one IP file. Only directly include the .ip file, not the .qip or .qsys.
  Error (22175): file: "top/ioc/ip/fcm2_adcs/clock_in_0.ip"
  Error (22175): file: "top/ioc/ip/fcm2_periph/clock_in_0.ip"
Error: Flow failed: 0x20c47a40
Error: Quartus Prime Synthesis was unsuccessful. 4 errors, 129 warnings
    Error: Peak virtual memory: 3496 megabytes
    Error: Processing ended: Wed Nov 12 09:58:48 2025
    Error: Elapsed time: 00:01:01
    Error: System process ID: 2072199
Error (21794): Quartus Prime Full Compilation was unsuccessful. 6 errors, 224 warnings
Error: Flow compile (for project integration/adc/O.quar.prod/fcm2) was not successful
Error: run_flow flow:run1 finished: 0 Failed
Error (23031): Evaluation of Tcl script /ade/fpga/altera/pro_22.4/quartus/common/tcl/internal/qsh_flowengine.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 13 errors, 224 warnings
    Error: Peak virtual memory: 1310 megabytes
    Error: Processing ended: Wed Nov 12 09:58:54 2025
    Error: Elapsed time: 00:03:54
    Error: System process ID: 2068912

3 Replies

  • JHill1's avatar
    JHill1
    Icon for Occasional Contributor rankOccasional Contributor

    Using Platform Designer to delete and recreate a newly added clock bridge, exactly the same as before including using the same block name and the same clock input export name, in my peripheral sub-component has fixed the issue.

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor

    Good to hear that. Could you help us tag the Quartus version and device used above? This information will assist us in performing analysis in the future.


     

  • JHill1's avatar
    JHill1
    Icon for Occasional Contributor rankOccasional Contributor

    Quartus Prime Version 22.4.0 build 94 12/07/2022 Pro Edition, no patches installed

    Platform Designer 22.4 Build 94

    Arrria10 device

    I have a tcl script that runs during the build, and adds the varios IP and QSYS components to the quartus project. I have to do this with newer ALtera versions because the same qsys system is used in multiple quartus projects.