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Honored ContributorError 10500: VHDL Syntax
I am working on a code for a basic vending machine that will give out a product at 75cents
BUt for some reason I dont know how to fix this syntax error
Library ieee;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Lab06 is
Port (
Clock :IN std_logic;
Reset_n :IN std_logic;
Quarter_in :IN std_logic;
Dime_in :IN std_logic;
Nickel_in :IN std_logic;
Pennny_in :IN std_logic;
Coin_Return :IN std_logic);
End Lab06;
Architecture Behavior Of Lab06 is
Signal int_counter: std_logic_vector(25 downto 0);
Constant MAXVALUE: std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count
-------------------------------------------------------------------------------------------------
Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change);
Signal current_state,next_state: state_type;
Signal Money: std_logic_vector(6 downto 0);
Signal Red_Bull: std_logic;
Signal Change_Back: std_logic;
Begin
Counter_Clock:Process (clock, reset_n)
Begin
If reset_n = '0' Then
Int_counter <= (Others => '0');
Elsif (rising_edge(clock)) Then
If int_counter = MAXVALUE Then
int_counter <= (Others => '0');
Else
int_counter <= int_counter + '1';
End If;
End If;
End Process;
Sync:Process (clock, reset_n)
Begin
If (reset_n = '0')then
Current_state <= Wait1;--Wait1 is the default state_type
Elsif(rising_edge(clock))Then
If (int_counter = MAXVALUE)Then
Current_state <=next_state;-- Advance the state(Red Bull)machine
End If;
End If;
End Process;
Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return)
Begin
If (int_counter = MAXVALUE) Then
Case(current_state)is
When wait1=>
If (money = "0000000")Then -- No money in vending machine
next_state <= Wait1;
If (Quarter_in = '1')Then -- Money is inserted
next_state <= Quarter;
If (Dime_in = '1')Then
next_state <= Dime;
If (Nickel_in = '1')Then
next_state <= Nickel;
If (Pennny_in = '1')Then
next_state <= Penny;
If (money >= "1001011")Then
next_state <= Enough;
If(Coin_Return = '1')Then
next_state <= Change;
Else
next_state <=Wait1;
End If;
----------------------------------------------------------------- After Quarter Inserted, next step
When Quarter =>
Next_state <= Wait1;
----------------------------------------------------------------- After Dime Inserted, next step
When Dime =>
Next_state <= Wait1;
----------------------------------------------------------------- After Nickel Inserted, next step
When Nickel =>
Next_state <= Wait1;
----------------------------------------------------------------- After Penny Inserted, next step
When Penny =>
Next_state <= Wait1;
When Enough =>
If (money >= "1001011")Then
Next_state <= Excess;
Else
Next_state <= vend;
End If;
When Excess =>
Next_state <= vend;
When vend =>
Next_state <= Wait1;
When Change =>
Next_state <= Wait1;
When OTHERS =>
next_state <= Wait1;
End Case;
End If;
End Process;
----------------------------------------------------------------- Money calculation
Money_Calc:Process(Current_state, money)
Begin
Case (current_state) is
When wait1 =>
Money <= Money;
When Quarter =>
Money <= Money + "0011001";
When Dime =>
Money <= Money + "0001010";
When Nickel =>
Money <= Money + "0000101";
When Penny =>
Money <= Money + "0000001";
When Enough =>
Money <= money;
When Excess =>
Money <= Money;
When vend =>
Money <= Money - "1001011";
When change =>
Money <= "0000000";
When OTHERS =>
Money <= Money;
End Case;
End Process;
End Behavior;
30 Replies
Altera_ForumYour first group of IFs in second process need to be elsif or end each one before going to next or you will lose all your money
- Altera_Forum
Wouldn't that make it nested?
- Altera_Forum
I had it like that before, and I didnot get errors. But it did cause warning latches.
Warning (10631): VHDL Process Statement warning at Lab06.vhd(84): inferring latch(es) for signal or variable "next_state", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at Lab06.vhd(138): inferring latch(es) for signal or variable "Money", which holds its previous value in one or more paths through the process Info (10041): Inferred latch for "Money[0]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[1]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[2]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[3]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[4]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[5]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[6]" at Lab06.vhd(138) Info (10041): Inferred latch for "next_state.change" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.vend" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.excess" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.enough" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.quarter" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.nickel" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.dime" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.penny" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.wait1" at Lab06.vhd(84)Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return) Begin If (int_counter = MAXVALUE) Then Case(current_state)is When wait1=> If (money = "0000000")Then -- No money in vending machine next_state <= Wait1; Elsif (Quarter_in = '1')Then -- Money is inserted next_state <= Quarter; Elsif (Dime_in = '1')Then next_state <= Dime; Elsif (Nickel_in = '1')Then next_state <= Nickel; Elsif (Pennny_in = '1')Then next_state <= Penny; Elsif (money >= "1001011")Then next_state <= Enough; Elsif(Coin_Return = '1')Then next_state <= Change; Else next_state <=Wait1; End If; ----------------------------------------------------------------- After Quarter Inserted, next step When Quarter => Next_state <= Wait1; ----------------------------------------------------------------- After Dime Inserted, next step When Dime => Next_state <= Wait1; ----------------------------------------------------------------- After Nickel Inserted, next step When Nickel => Next_state <= Wait1; ----------------------------------------------------------------- After Penny Inserted, next step When Penny => Next_state <= Wait1; When Enough => If (money >= "1001011")Then Next_state <= Excess; Else Next_state <= vend; End If; When Excess => Next_state <= vend; When vend => Next_state <= Wait1; When Change => Next_state <= Wait1; When OTHERS => next_state <= Wait1; End Case; End If; End Process; - Altera_Forum
If you want it nested then use "elsif" from second one and finish last "elsif" by "end if". That way priority is given in that order. If you end each if separately then priority is reverse if following statement drives samenode.
- Altera_Forum
I am sorry that I dont understand what you just said, but I don't need it to be nested. Should it be elsif or if?
- Altera_Forum
in the firt case of the state machine, you are opening like 7 if conditions but you only closes one of them!
- Altera_Forum
If you don't want latches then either use clock edge so creating registers or keep it as it is but define what should happen if int_count is not max value. And any other areas.
The decision to drive the next state is up to the way you want it to be. If you use elsif as you have done then priority is given to first test and if not true then moves to next... - Altera_Forum--- Quote Start --- in the firt case of the state machine, you are opening like 7 if conditions but you only closes one of them! --- Quote End --- Yeah I originally had elsif and had a bunch of inferred latches and he told me to swap it for if and a whole bunch of new errors happened. This is the code I have now
And I have a bunch of inferred latches Info (10041): Inferred latch for "Money[0]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[1]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[2]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[3]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[4]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[5]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[6]" at Lab06.vhd(138) Info (10041): Inferred latch for "next_state.change" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.vend" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.excess" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.enough" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.quarter" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.nickel" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.dime" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.penny" at Lab06.vhd(84) Info (10041): Inferred latch for "next_state.wait1" at Lab06.vhd(84)--*************************** VHDL Source Code****************************** --********* Copyright 2012, Rochester Institute of Technology*************** --*************************************************************************** -- -- DESIGNER NAME: <Fabian James> -- -- LAB NAME: <lab# 06> -- -- FILE NAME: <Lab06> -- ------------------------------------------------------------------------------- -- -- DESCRIPTION -- -- -- -- ------------------------------------------------------------------------------- -- -- REVISION HISTORY -- -- _______________________________________________________________________ -- | DATE | USER | Ver | Description | -- |==========+=======+=====+================================================ -- | | | | -- | 10/30/12 |Creator| 1.0 | Start of coding -- | | | | -- -- --*************************************************************************** --*************************************************************************** Library ieee; Use ieee.numeric_std.all; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity Lab06 is Port ( Clock :IN std_logic; Reset_n :IN std_logic; Quarter_in :IN std_logic; Dime_in :IN std_logic; Nickel_in :IN std_logic; Pennny_in :IN std_logic; Coin_Return :IN std_logic); End Lab06; Architecture Behavior Of Lab06 is Signal int_counter: std_logic_vector(25 downto 0); Constant MAXVALUE: std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count ------------------------------------------------------------------------------------------------- Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change); Signal current_state,next_state: state_type; Signal Money: std_logic_vector(6 downto 0); Signal Red_Bull: std_logic; Signal Change_Back: std_logic; Begin Counter_Clock:Process (clock, reset_n) Begin If reset_n = '0' Then Int_counter <= (Others => '0'); Elsif (rising_edge(clock)) Then If int_counter = MAXVALUE Then int_counter <= (Others => '0'); Else int_counter <= int_counter + '1'; End If; End If; End Process; Sync:Process (clock, reset_n) Begin If (reset_n = '0')then Current_state <= Wait1;--Wait1 is the default state_type Elsif(rising_edge(clock))Then If (int_counter = MAXVALUE)Then Current_state <=next_state;-- Advance the state(Red Bull)machine End If; End If; End Process; Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return) Begin If (int_counter = MAXVALUE) Then Case(current_state)is When wait1=> If (money = "0000000")Then -- No money in vending machine next_state <= Wait1; Elsif (Quarter_in = '1')Then -- Money is inserted next_state <= Quarter; Elsif (Dime_in = '1')Then next_state <= Dime; Elsif (Nickel_in = '1')Then next_state <= Nickel; Elsif (Pennny_in = '1')Then next_state <= Penny; Elsif (money >= "1001011")Then next_state <= Enough; Elsif(Coin_Return = '1')Then next_state <= Change; Else next_state <=Wait1; End If; ----------------------------------------------------------------- After Quarter Inserted, next step When Quarter => Next_state <= Wait1; ----------------------------------------------------------------- After Dime Inserted, next step When Dime => Next_state <= Wait1; ----------------------------------------------------------------- After Nickel Inserted, next step When Nickel => Next_state <= Wait1; ----------------------------------------------------------------- After Penny Inserted, next step When Penny => Next_state <= Wait1; When Enough => If (money >= "1001011")Then Next_state <= Excess; Else Next_state <= vend; End If; When Excess => Next_state <= vend; When vend => Next_state <= Wait1; When Change => Next_state <= Wait1; When OTHERS => next_state <= Wait1; End Case; End If; End Process; ----------------------------------------------------------------- Money calculation Money_Calc:Process(Current_state, money) Begin Case (current_state) is When wait1 => Money <= Money; When Quarter => Money <= Money + "0011001"; When Dime => Money <= Money + "0001010"; When Nickel => Money <= Money + "0000101"; When Penny => Money <= Money + "0000001"; When Enough => Money <= money; When Excess => Money <= Money; When vend => Money <= Money - "1001011"; When change => Money <= "0000000"; When OTHERS => Money <= Money; End Case; End Process; End Behavior; - Altera_Forum
May be, you prefer the process that control state machine this way:
process(.... begin next_state <= Current_state; case.... So, by default the state machine preserves current state, and avoid unintented latches. If a condition in the case matches, then next_state will be modified. - Altera_Forum
Ok I am struggling to keep up with all th idea everyone is saying. (WHICH IS GOOD it is helping out alot and thank you)
--- Quote Start --- If you don't want latches then either use clock edge so creating registers or keep it as it is but define what should happen if int_count is not max value. And any other areas. The decision to drive the next state is up to the way you want it to be. If you use elsif as you have done then priority is given to first test and if not true then moves to next... --- Quote End --- That worked out well to remove the latches from the first case. And now I have a problem of my vector money -It is tested in two process which I know is bad but I am not sure how to start or add to my code to fix it Once again here is the current code
And here are my new errors Warning (10492): VHDL Process Statement warning at Lab06.vhd(142): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(144): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(146): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(148): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(150): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(152): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(154): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(156): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10492): VHDL Process Statement warning at Lab06.vhd(160): signal "Money" is read inside the Process Statement but isn't in the Process Statement's sensitivity list Warning (10631): VHDL Process Statement warning at Lab06.vhd(138): inferring latch(es) for signal or variable "Money", which holds its previous value in one or more paths through the process Info (10041): Inferred latch for "Money[0]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[1]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[2]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[3]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[4]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[5]" at Lab06.vhd(138) Info (10041): Inferred latch for "Money[6]" at Lab06.vhd(138)Library ieee; Use ieee.numeric_std.all; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity Lab06 is Port ( Clock :IN std_logic; Reset_n :IN std_logic; Quarter_in :IN std_logic; Dime_in :IN std_logic; Nickel_in :IN std_logic; Pennny_in :IN std_logic; Coin_Return :IN std_logic); End Lab06; Architecture Behavior Of Lab06 is Signal int_counter: std_logic_vector(25 downto 0); Constant MAXVALUE: std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count ------------------------------------------------------------------------------------------------- Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change); Signal current_state,next_state: state_type; Signal Money: std_logic_vector(6 downto 0); Signal Red_Bull: std_logic; Signal Change_Back: std_logic; Begin Counter_Clock:Process (clock, reset_n) Begin If reset_n = '0' Then Int_counter <= (Others => '0'); Elsif (rising_edge(clock)) Then If int_counter = MAXVALUE Then int_counter <= (Others => '0'); Else int_counter <= int_counter + '1'; End If; End If; End Process; Sync:Process (clock, reset_n) Begin If (reset_n = '0')then Current_state <= Wait1;--Wait1 is the default state_type Elsif(rising_edge(clock))Then If (int_counter = MAXVALUE)Then Current_state <=next_state;-- Advance the state(Red Bull)machine End If; End If; End Process; Comb:Process(clock,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return) Begin If (rising_edge(clock)) Then Case(current_state)is When wait1=> If (money = "0000000")Then -- No money in vending machine next_state <= Wait1; Elsif (Quarter_in = '1')Then -- Money is inserted next_state <= Quarter; Elsif (Dime_in = '1')Then next_state <= Dime; Elsif (Nickel_in = '1')Then next_state <= Nickel; Elsif (Pennny_in = '1')Then next_state <= Penny; Elsif (money >= "1001011")Then next_state <= Enough; Elsif(Coin_Return = '1')Then next_state <= Change; Else next_state <=Wait1; End If; ----------------------------------------------------------------- After Quarter Inserted, next step When Quarter => Next_state <= Wait1; ----------------------------------------------------------------- After Dime Inserted, next step When Dime => Next_state <= Wait1; ----------------------------------------------------------------- After Nickel Inserted, next step When Nickel => Next_state <= Wait1; ----------------------------------------------------------------- After Penny Inserted, next step When Penny => Next_state <= Wait1; When Enough => If (money >= "1001011")Then Next_state <= Excess; Else Next_state <= vend; End If; When Excess => Next_state <= vend; When vend => Next_state <= Wait1; When Change => Next_state <= Wait1; When OTHERS => next_state <= Wait1; End Case; End If; End Process; ----------------------------------------------------------------- Money calculation Money_Calc:Process(Current_state,money) Begin Case (current_state) is When wait1 => Money <= Money; When Quarter => Money <= Money + "0011001"; When Dime => Money <= Money + "0001010"; When Nickel => Money <= Money + "0000101"; When Penny => Money <= Money + "0000001"; When Enough => Money <= money; When Excess => Money <= Money; When vend => Money <= Money - "1001011"; When change => Money <= "0000000"; When OTHERS => Money <= Money; End Case; End Process; End Behavior;
