--- Quote Start ---
in the firt case of the state machine, you are opening like 7 if conditions but you only closes one of them!
--- Quote End ---
Yeah I originally had elsif and had a bunch of inferred latches and he told me to swap it for if and a whole bunch of new errors happened. This is the code I have now
--*************************** VHDL Source Code******************************
--********* Copyright 2012, Rochester Institute of Technology***************
--***************************************************************************
--
-- DESIGNER NAME: <Fabian James>
--
-- LAB NAME: <lab# 06>
--
-- FILE NAME: <Lab06>
--
-------------------------------------------------------------------------------
--
-- DESCRIPTION
--
--
--
--
-------------------------------------------------------------------------------
--
-- REVISION HISTORY
--
-- _______________________________________________________________________
-- | DATE | USER | Ver | Description |
-- |==========+=======+=====+================================================
-- | | | |
-- | 10/30/12 |Creator| 1.0 | Start of coding
-- | | | |
--
--
--***************************************************************************
--***************************************************************************
Library ieee;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Lab06 is
Port (
Clock :IN std_logic;
Reset_n :IN std_logic;
Quarter_in :IN std_logic;
Dime_in :IN std_logic;
Nickel_in :IN std_logic;
Pennny_in :IN std_logic;
Coin_Return :IN std_logic);
End Lab06;
Architecture Behavior Of Lab06 is
Signal int_counter: std_logic_vector(25 downto 0);
Constant MAXVALUE: std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count
-------------------------------------------------------------------------------------------------
Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change);
Signal current_state,next_state: state_type;
Signal Money: std_logic_vector(6 downto 0);
Signal Red_Bull: std_logic;
Signal Change_Back: std_logic;
Begin
Counter_Clock:Process (clock, reset_n)
Begin
If reset_n = '0' Then
Int_counter <= (Others => '0');
Elsif (rising_edge(clock)) Then
If int_counter = MAXVALUE Then
int_counter <= (Others => '0');
Else
int_counter <= int_counter + '1';
End If;
End If;
End Process;
Sync:Process (clock, reset_n)
Begin
If (reset_n = '0')then
Current_state <= Wait1;--Wait1 is the default state_type
Elsif(rising_edge(clock))Then
If (int_counter = MAXVALUE)Then
Current_state <=next_state;-- Advance the state(Red Bull)machine
End If;
End If;
End Process;
Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return)
Begin
If (int_counter = MAXVALUE) Then
Case(current_state)is
When wait1=>
If (money = "0000000")Then -- No money in vending machine
next_state <= Wait1;
Elsif (Quarter_in = '1')Then -- Money is inserted
next_state <= Quarter;
Elsif (Dime_in = '1')Then
next_state <= Dime;
Elsif (Nickel_in = '1')Then
next_state <= Nickel;
Elsif (Pennny_in = '1')Then
next_state <= Penny;
Elsif (money >= "1001011")Then
next_state <= Enough;
Elsif(Coin_Return = '1')Then
next_state <= Change;
Else
next_state <=Wait1;
End If;
----------------------------------------------------------------- After Quarter Inserted, next step
When Quarter =>
Next_state <= Wait1;
----------------------------------------------------------------- After Dime Inserted, next step
When Dime =>
Next_state <= Wait1;
----------------------------------------------------------------- After Nickel Inserted, next step
When Nickel =>
Next_state <= Wait1;
----------------------------------------------------------------- After Penny Inserted, next step
When Penny =>
Next_state <= Wait1;
When Enough =>
If (money >= "1001011")Then
Next_state <= Excess;
Else
Next_state <= vend;
End If;
When Excess =>
Next_state <= vend;
When vend =>
Next_state <= Wait1;
When Change =>
Next_state <= Wait1;
When OTHERS =>
next_state <= Wait1;
End Case;
End If;
End Process;
----------------------------------------------------------------- Money calculation
Money_Calc:Process(Current_state, money)
Begin
Case (current_state) is
When wait1 =>
Money <= Money;
When Quarter =>
Money <= Money + "0011001";
When Dime =>
Money <= Money + "0001010";
When Nickel =>
Money <= Money + "0000101";
When Penny =>
Money <= Money + "0000001";
When Enough =>
Money <= money;
When Excess =>
Money <= Money;
When vend =>
Money <= Money - "1001011";
When change =>
Money <= "0000000";
When OTHERS =>
Money <= Money;
End Case;
End Process;
End Behavior;
And I have a bunch of inferred latches
Info (10041): Inferred latch for "Money[0]" at Lab06.vhd(138)
Info (10041): Inferred latch for "Money[1]" at Lab06.vhd(138)
Info (10041): Inferred latch for "Money[2]" at Lab06.vhd(138)
Info (10041): Inferred latch for "Money[3]" at Lab06.vhd(138)
Info (10041): Inferred latch for "Money[4]" at Lab06.vhd(138)
Info (10041): Inferred latch for "Money[5]" at Lab06.vhd(138)
Info (10041): Inferred latch for "Money[6]" at Lab06.vhd(138)
Info (10041): Inferred latch for "next_state.change" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.vend" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.excess" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.enough" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.quarter" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.nickel" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.dime" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.penny" at Lab06.vhd(84)
Info (10041): Inferred latch for "next_state.wait1" at Lab06.vhd(84)
Honored Contributor
