Hello to everybody, could someone tell me what's wrong in the following code? library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity round16to12 is port ( a : in std_logic_vector(15 downto 0); q : out std_logic_vector(11 downto 0) ); end entity; architecture beh of round16to12 is signal roundoff : std_logic_vector(11 downto 0) := (0 => a(3), others => '0'); begin process(a) begin line 23: q <= (not( a(15)) & a(14 downto 4)) + roundoff; end process; end beh; The error message is the following: Error (10327): VHDL error at round16to12.vhd(23): can't determine definition of operator ""+"" -- found 0 possible definitions Thank for your support

Hello, addtion isn't defined for std_logic_vector. You can use explicite numeric types SIGNED or UNSIGNED. Alternatively you can use a library that treats all std_logic_vector as SIGNED or UNSIGNED type: IEEE.STD_LOGIC_SIGNED respectively IEEE.STD_LOGIC_UNSIGNED. Regards, Frank B.T.W: I see this message every time, when I start writing a new component. It's cause VHDL is so strictly typified.

To add to what Frank said, if you are doing arithmetic, it is quicker (simulation-wise) to use INTEGER types, rather than vectors of bits. Other things that you get from this are errors if you use restricted ranges of integer and it goes outside of the range. This does mean that if you want modulo-n rollover in a counter or similar, you have to code it explicitly: if (counter + 1 > t_counter'high) then counter := 0; else counter := counter +1; end if; If t_counter'high is a power of 2, then the "counter+1>" comparison will usually optimise out in synthesis. Cheers, Martin

If you use integer types, declare each object with a specific range if possible. Integer types require 32-bits in Quartus II. If you simply add two integer objects, you'll get a 32-bit adder initially, which Quartus II may or may not be able to optimize fully. For sure, it won't always find the solution you can get by simply defining the appropriate dynamic range for each object. It will certainly improve the compile-time/memory use in Quartus II! I generally use signed/unsigned from ieee.numeric_std, using integer types only for very limited purposes, such as array indices (it's a pain to convert from signed/unsigned to integer all the time :)

Does Quartus not optimise based on reachability analysis? If I code a counter that wraps around at 255, does it not infer an 8-bit counter? I know Max Plus II never did, but surely Quartus can do this... Also, why do you say use signed/unsigned all the time? Most of the time, you only *need* vectors for the top level port pins. Just pass integers around your design hierarchy the rest of the time. Typing to_integer() isn't that much grief anyway is it? :-)? All IMHO of course! Cheers, Martin

Alternatively use LPM_ADD_SUB, more code to write but less chance of something being misinterpreted than with a +

Error 10327: Can't determine definition of operator ""+""

30 Replies

Altera_Forum
Honored Contributor
12 years ago
you havent shown the definition of ARRAY32TO3 type.
Altera_Forum
Honored Contributor
12 years ago
Actually, y_den is a single signed number, not an array of signed. Y_den(0) is a single bit - you cannot add that to a signed.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Actually, y_den is a single signed number, not an array of signed. Y_den(0) is a single bit - you cannot add that to a signed.
--- Quote End ---

Oh.. Yes..sorry. i forget to post the first file.. with the definition of subtype and type.. so i correct y_den into array32to2 but the error of "+" don't change..

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;

PACKAGE width_bit_signed IS
SUBTYPE BITS16 IS signed(15 downto 0) ; --11bit
SUBTYPE BITS32 IS signed(31 downto 0); --22bit

TYPE ARRAY16TO3 IS ARRAY (0 TO 2) OF BITS16;
TYPE ARRAY32TO2 IS ARRAY (0 TO 1) OF BITS32;
TYPE ARRAY32TO3 IS ARRAY (0 TO 2) OF BITS32;
END width_bit_signed;

Mh... i compile this program last week and it function ..then i change the size of the register into 11 and 22 bit instead of 16 and 32 and it don't function so i rewrite the original program with 16 and 32 bit but.. there is alway the error that don't recognize "+" why????:confused::(
thank for your response Tricky..
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Oh.. Yes..sorry. i forget to post the first file.. with the definition of subtype and type.. so i correct y_den into array32to2 but the error of "+" don't change..

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;

PACKAGE width_bit_signed IS
SUBTYPE BITS16 IS signed(15 downto 0) ; --11bit
SUBTYPE BITS32 IS signed(31 downto 0); --22bit

TYPE ARRAY16TO3 IS ARRAY (0 TO 2) OF BITS16;
TYPE ARRAY32TO2 IS ARRAY (0 TO 1) OF BITS32;
TYPE ARRAY32TO3 IS ARRAY (0 TO 2) OF BITS32;
END width_bit_signed;

Mh... i compile this program last week and it function ..then i change the size of the register into 11 and 22 bit instead of 16 and 32 and it don't function so i rewrite the original program with 16 and 32 bit but.. there is alway the error that don't recognize "+" why????:confused::(
thank for your response Tricky..
--- Quote End ---

at 19:40 i resolve my problem when i rewrite i don't put y like an array but only single register..
sorry.. i'm tired.. all day in front of the pc.. and so i write crazy code...
Thank you Tricky!:-P
Can i engage you like my personal debugger??? :o
Altera_Forum
Honored Contributor
10 years ago
i've got the same error for the operator "-". Using signed type and ieee.numeric_std. I would like to ask if my usage of "for" is correct.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use ieee.numeric_std.all;

entity stage_1 is
Port (
clk : in bit;
imagem: in SIGNED (19999 DOWNTO 0);
imagemanterior: in SIGNED (19999 DOWNTO 0);
Ix: out SIGNED (24999 DOWNTO 0);
Iy: out SIGNED (24999 DOWNTO 0);
It: out SIGNED (24999 DOWNTO 0)
);
end stage_1;

architecture Behavioral of stage_1 is
begin

process (clk)
begin
If (clk 'event and clk = '1') then

for I in 0 to 2448 loop
Ix(I*10+9 DOWNTO I*10) <= 1/4 * (imagemanterior((I+1)*8+7 DOWNTO (I+1)*8) - imagemanterior(I*8+7 DOWNTO I*8) + imagemanterior ((I+1)*8+407 DOWNTO (I+1)*8+400) - imagemanterior(I*8+407 DOWNTO I*8+400) + imagem((I+1)*8+7 DOWNTO(I+1)*8) - imagem(I*8+7 DOWNTO I*8)+ imagem((I+1)*8+407 DOWNTO(I+1)*8) - imagem((I)*8+407 DOWNTO I*8 +400));
Iy(I*10+9 DOWNTO I*10) <= 1/4*(imagemanterior((I*8)+407 DOWNTO (I)*8+400) - imagemanterior(I*8+7 DOWNTO I*8) + imagemanterior((I+1)*8+407 DOWNTO (I+1)*8) - imagemanterior((I+1)*8+7 DOWNTO(I+1)*8) + imagem(I*8+407 DOWNTO I*8+400) - imagem(I*8+7 DOWNTO I*68) + imagem((I+1)*8+407 DOWNTO (I+1)*8+400) -imagem((I+1)*8+7 DOWNTO(I+1)*8));
It(I*10+9 DOWNTO I*10) <= 1/4 * (imagem(I*8+7 DOWNTO I*8)- imagemanterior((I*8+7)-I*8) + imagem((I*8)+407 DOWNTO I*8+400)- imagemanterior(I*8+407 DOWNTO I*8+400) +imagem((I+1)*8+7 DOWNTO(I+1)*8)- imagemanterior((I+1)*8+7 DOWNTO(I+1)*8) + imagem((I+1)*8+407 DOWNTO (I+1)*8+400)- imagemanterior((I+1)*8+407 DOWNTO (I+1)*8+400));

end loop;

end if ;

end process;

end Behavioral;
Altera_Forum
Honored Contributor
10 years ago
wow - those are possibly the largest busses I have ever seen
Why have you got busses so wide?
Plus there are many problems.
1/4 = 0 when it is rounded down.
Why do you have such a massive for loop?
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
wow - those are possibly the largest busses I have ever seen
Why have you got busses so wide?
Plus there are many problems.
1/4 = 0 when it is rounded down.
Why do you have such a massive for loop?
--- Quote End ---

My idea was to implement the same architecture for pixels (0,0) to (48,48) arriving at the same time in a 50x50 image. Replacing the 1/4 by a division would solve the issue?

Thanks.
Altera_Forum
Honored Contributor
10 years ago
Almost definately not.
How do you expect a 50x50 image to arrive at the same time? why did you make some massive array of unsigned? why not just a 2d array of unsigned:

type image_array_t is array(0 to 49, 0 to 49) of unsigned(7 downto 0); signal my_image : image_array_t; for x in my_image'range(1) loop for y in my_image'range(2) loop my_image(x,y) <= something; end loop end loop;

But if you expect a 50x50 image to just magically appear, I suspect there is something more fundamentally wrong with your design than a '-' function not working. The error you had will be because you sliced something wrong somewhere (and because it is rather hideous to look at I cant be bothered to find it right now)
Altera_Forum
Honored Contributor
10 years ago
i've got the error for the operator ""-"" in the following code. I'm not sure about accessing the indivdual bits of each unsigned in the array.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use Ieee.numeric_std.all;

use work.genetica_type.all;

entity binario_fitness is
Port (
clk : in std_logic;
individuos: in genetica;
adaptacao: out fitness;
somafitness: out unsigned (7 downto 0)
);
end binario_fitness;

architecture Behavioral of binario_fitness is
begin

process (clk)
begin
If (clk 'event and clk = '1') then

for x in 0 to 49 loop

adaptacao(x) <= individuos(x)(0)-individuos(x)(1) +individuos(x)(2)- individuos(x)(3)+individuos(x)(4)- individuos(x)(5)+individuos(x)(6)-individuos(x)(7);
somafitness<=(others=>'0');
end loop;

end if ;

end process;

end Behavioral;
which includes the genetica_type in another file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use ieee.numeric_std.all;

package genetica_type is
type genetica is array(0 to 49) of unsigned(7 downto 0);
type fitness is array(0 to 49) of unsigned (2 downto 0);
end package genetica_type;
Altera_Forum
Honored Contributor
10 years ago
Why are you trying to access individual bits of a number? You cannot sum them as they are just std_logic so no arithmetic is defined for them.

I think you need to make a function to count the bits for you.

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Error 10327: Can't determine definition of operator ""+""

30 Replies

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