Efficient State Machine Design

For reference, I would recommend the O.P. read the Quartus Tools Handbook for the version they are using, specifically Volume 1: Design and Synthesis, Chapter 16, Synthesis Options, State Machine Processing. For v16.0.0 (which I am using) this is on page 16-30, but will depend slightly on the specific tool version, I suspect. It describes how the default state machine (re)encoding for FPGAs is "one-hot", but other options are "sequential", "gray", "johnson", "compact", and "user". You can add an attribute (syn_encoding) to the state register definition to specify the specific state machine encoding desired. Or set the syn_encoding default to be, instead of "auto", to be "user" to force quartus to leave your state machine designs as is.