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khagesh1010's avatar
khagesh1010
Icon for New Contributor rankNew Contributor
2 years ago

E-tile Clock management

Hi, I am using Agilex -7 with 1 Etile & Ptile version. On E-tile i have to interface 10G ethernet IP and JESD204B IP both. For 10G ethernet 156.25MHz clock is mapped on REFCLK[7] and for JESD204B 15...
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ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Khagesh,


Your clock mapping should be fine because pin used was same as the example design.


Best regards,

zying