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khagesh1010's avatar
khagesh1010
Icon for New Contributor rankNew Contributor
2 years ago

E-tile Clock management

Hi,

I am using Agilex -7 with 1 Etile & Ptile version. On E-tile i have to interface 10G ethernet IP and JESD204B IP both. For 10G ethernet 156.25MHz clock is mapped on REFCLK[7] and for JESD204B 150MHz clock is mapped on REFCLK[0] of BANK 9A.

i just want to know
1. whether this assignment of clock is OK? - I need to give priority to JESD204B .

2. Or 10G is require the REFCLK[0] for initial configuration of PMA?

Please confirm clock mapping.

--

Khagesh Khandelwal

Hdl
Platform

5 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    May I know the FPGA OPN number that you use?


    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi Khagesh,


    Your clock mapping should be fine because pin used was same as the example design.


    Best regards,

    zying



  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    Hi,


    Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Best regards,

    zying