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Altera_Forum's avatar
Altera_Forum
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15 years ago

Dual-Purpose Pins in Quartus 10.0

Hello there,

i have switched my project from Quartus 8.2 to Quartus 10.0

My Configuration scheme is Active Parallel.

(Active Serial has the same problem).

After Device configuration i want to use the configuration pins as regular IO's.

My Problem:

Under Quartus V10.0 i can not set the Dual-Purpose Pins to "Use as regular I/O".

DCLK can only set to "Use as programming pin"

Data[1]/ASDO can only set to "As input tri-stated"

Data[7..2] can only set to "As input tri-stated"

FLASH_nCE/nCSO can only set to "As input tri-stated"

Other Active Parallel pins can only set to "As input tri-stated"

Is this a Quartus 10.0 problem ?

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As a temporary workaround, you can try to specify a different configuration scheme in device configuration (e.g. PS), but actually use AS. I had to use this solution in some cases with previous Quartus revisions.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    As a temporary workaround, you can try to specify a different configuration scheme in device configuration (e.g. PS), but actually use AS. I had to use this solution in some cases with previous Quartus revisions.

    --- Quote End ---

    Thanks,

    i have set the configuration scheme to PS.

    Now i can set all pins to "Use as regular I/O".

    exeptionn DCLK. DCLK still can only set to "Use as programming pin".

    Compilation is aborded with the message:

    Error: Can't place multiple pins assigned to pin location Pin_K2 (IOPAD_X0_Y27_N14)

    Info: Pin dclk is assigned to pin location Pin_K2 (IOPAD_X0_Y27_N14)

    Info: Pin ~ALTERA_DCLK~ is assigned to pin location Pin_K2 (IOPAD_X0_Y27_N14)

    So i still can not use the EPCS Controller in my design, because i can not set all general purpose pins to "Use as Regular I/O"
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The same problem here... That's the very reason why I gave up 10.0 and turn back to 9.1 sp1... I cannot set DCLK to regular I/O with any configuration... That's really frustrated

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    That's the risk of a "first implementer". Because I don't use Cyclone IV yet, I staid with V9.0 and "missed" a lot of bugs newly introduced with V9.1.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    it might be just a GUI issue. try adding the following line to your .qsf:

    set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks, great idea.

    It is a GUI issue. If i set the assignments as follow in the .qsf before i compile the design, there is no error and the fitter completes his job.

    set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Thanks, great idea.

    It is a GUI issue. If i set the assignments as follow in the .qsf before i compile the design, there is no error and the fitter completes his job.

    set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"

    --- Quote End ---

    I have try this mathod, but I can not access the epcs still.(I can read epsc when i use Quartus 9.0)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    I have try this mathod, but I can not access the epcs still.(I can read epsc when i use Quartus 9.0)

    --- Quote End ---

    Same here. I'm using a EP4C115F23C8 with Quartus II 10.0 SP1. As recommended, I added the following lines to the .qsf file:

    set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"

    set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"

    With SignalTap I can see the correct waveforms on FLASH_CE#, DCLK and ASDO, but DATA0 is always high.

    If I measure on the hardware, I see the corresponding waveforms on FLASH_CE#, ASDO and DATA0. but dclk is always high (all signals have external pull-ups). As DCLK behaves differently between SignalTap and hardware, I assume that the DCLK FPGA Pin actually is in high-impedance state.

    The Pin-Out File tells this:

    Pin Name/Usage : Location : Dir. : I/O Standard : Volt. : Bank : Usr. ***.

    Fpga_Dclk : K2 : output : 3.3-V LVCMOS : : 1 : Y

    So one could assume that everything is ok, but it obviously is not. Going back to Quartus 9.x is no option because the 9.x EPCS Flash Controller does not work with Cyclone IV devices. Any ideas around?