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BIdro's avatar
BIdro
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Driver Dedicated Transceiver Pin

Hi,

I'm using Quartus Prime Software to program a Cyclone V GT FPGA.

I want to drive a differential pair of dedicated transceiver pins ( for example transmit a signal clock or packets without any IP). How can I do that?

Thanks for the help.

Bryan

  • Deshi_Intel's avatar
    Deshi_Intel
    5 years ago

    HI Bryan,


    Your questions is too high level but let me try my best to answer.


    In general, I advise you to checkout the IP in user guide doc first as different IP solution may have its own design requirement.


    Now to your questions

    1. In the Cyclone V family, is the IP compatible with GT/GX only?
    • The IP can be used for both GT/GX channel.
      • Main difference is the supported data rate
    1. When I use the IP, do I also have to define time constrains?
    • The IP already has its own timing constraint but you still need to constraint your FPGA core own design logic path that interact/connect with the IP block.


    Thanks.


    Regards,

    dlim


3 Replies

    • BIdro's avatar
      BIdro
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi Dlim,

      thank you for the response.

      Ok, I will use the IP but I have 2 questions:

      1) In the Cyclone V family, is the IP compatible with GT/GX only?

      2) When I use the IP, do I also have to define time constrains?

      Thanks.

      Bryan

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI Bryan,


    Your questions is too high level but let me try my best to answer.


    In general, I advise you to checkout the IP in user guide doc first as different IP solution may have its own design requirement.


    Now to your questions

    1. In the Cyclone V family, is the IP compatible with GT/GX only?
    • The IP can be used for both GT/GX channel.
      • Main difference is the supported data rate
    1. When I use the IP, do I also have to define time constrains?
    • The IP already has its own timing constraint but you still need to constraint your FPGA core own design logic path that interact/connect with the IP block.


    Thanks.


    Regards,

    dlim