New ContributorHi,
I am synthesizing Systemverilog RTL which has export construct in it and is not supported by Synplify. I wonder if any one has faced this issue and what workaround can be used.
Does Quartus support export construct from Systemverilog?
Thanks,
Ruturaj.
Regular ContributorHi,
May I know which edition of the software you are using?
According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf, the Intel Quartus Prime Standard/Lite edition software have limited SystemVerilog language support.
May I know what export you are referring to? Could you provide an example? Besides this, you can check the SystemVerilog synthesis support for Pro edition software in https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_list_sys_vlog.htm.
Thanks.
Best regards,
KhaiY
New ContributorHi KhaiY,
I am actually getting error in Synplify tool as it does not support export. I have not tried the code in Quartus yet. Below is the export of package which is present in RTL.
export cha_cms_mesh_pkg::*;
export cha_cms_mesh_pkg::AD_ADD_ADR_LSB;
I did check SystemVerilog synthesis support page of Quartus and it does not mention export.
I am using Quartus Prime Pro 18.1 and want to know if export is supported by Quartus.
Thanks,
Ruturaj.
Regular ContributorHi Ruturaj,
Upon testing, this is supported in the Pro edition but not Standard edition.
Thanks.
Best regards,
KhaiY
New ContributorHi KhaiY,
Thank you for testing and responding. I will tryout at my end.
Thanks,
Ruturaj.
Regular ContributorHi,
Sure. Please let me know if you have any questions.
Thanks.
Best regards,
KhaiY
Regular ContributorHi,
Do you have any updates?
Thanks.
Best regards,
KhaiY
New Contributor
