Does Quartus support VHDL external names in synthesis code?

Question

I am using Quartus Prime 18.0 Standard Edition. I have changed the Quartus settings to use VHDL 2008.

I have a line of code to access a signal buried inside the design at top level.

The design simply does not compile with it at all.

alias HSOT_ENABLE is <<signal WS_I.u0.host_interface_0.LAYER_7.ENABLE_STORED(0) : std_logic>>;

I keep getting this error:

Error (10500): VHDL syntax error at TOP_LEVEL.vhd(275) near text "<"; expecting an identifier, or a string literal

Are VHDL external names supposed to synthesize in Quartus?

ideyn · Answer

Hi gyuunyuu!As I know, Quartus Standard edition has a limited support for VHDL 2008. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/br/br-quartus-prime-software.pdfSo it's a good idea to try the same using Pro version of quartus.--Best regards,Ivan

gyuunyuu · Answer

I do not have license for the pro version. No one here considers it important enough to get license for it.

I basically tried to use "Signal Probe Pins" tool to drive this signal to an output pin for debug purpose. Basically the signal probe compilation gets stuck at 7% and remains there forever. Thus, I tried to use the VHDL external names. However, that is also not working here.

ideyn · Answer

As about your issue, you can check if it is available a 30 day trial version for Quartus Pro version just for test.Did you try signal tap this signal?--Best regards,Ivan

gyuunyuu · Answer

See, the signal goes to an FPGA pin and then goes through a huge amount of logic until it reaches the design portion where it invokes an action. The problem is that, when the signal is deasserted at the FPGA pin, there is several ms delay until the expected action is invoked by the design. This signal is supposed to cause immediate action when deasserted. Therefore, I suspect that the huge latency is coming from the all the logic that this signal passes through. I need to prove this to my boss. Therefore, I need to show him the external signal going into the FPGA, and the version that goes into specific part of the design to invoke an action, side by side.Signal tap won't have enough depth to show the two signals side by side for several ms.

ideyn · Answer

Well, ok, I got it. You need to write a long sequence of data, and you can't use signal tap acquisition directly.Well, ok, there some other variants.First of all it is possible to use Storage qualifier feature, if there are some long idle states during acquisition when changing type from Continuous acquisition to for example transitional you probably will manage to acquire all the changes.Secondly, you maybe can decrease sample clock frequency so signal tap could fit into the FPGA.Finally, you could use segmented type of acquisition (similar effect as with clock freq decreasing)Hope that helps.--Best regards,Ivan

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Does Quartus support VHDL external names in synthesis code?

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