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gyuunyuu's avatar
gyuunyuu
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6 years ago

Does Quartus support VHDL external names in synthesis code?

I am using Quartus Prime 18.0 Standard Edition. I have changed the Quartus settings to use VHDL 2008.​ I have a line of code to access a signal buried inside the design at top level. The design sim...
gyuunyuu's avatar
gyuunyuu
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6 years ago

I do not have license for the pro version. No one here considers it important enough to get license for it.

I basically tried to use "Signal Probe Pins" tool to drive this signal to an output pin for debug purpose. Basically the signal probe compilation gets stuck at 7% and remains there forever. Thus, I tried to use the VHDL external names. However, that is also not working here.

IDeyn's avatar
IDeyn
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6 years ago

As about your issue, you can check if it is available a 30 day trial version for Quartus Pro version just for test.

Did you try signal tap this signal?

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Best regards,

Ivan