Does modelsim_ae 15.1 support sparse memories?

A sparse memory is a large memory (reg [7:0] mem[(16*1024*1024):0]) where only a few locations are accessed during simulation.

Before SystemVerilog simulators were able to deal with this and not require a large amount of memory to be allocated on the host system. (VCS and NCsim deal with this automatically.)

This has also been called "dynamic memory".

Here is a link that explains the SV way to do it:

http://www.asicguru.com/system-verilog/tutorial/assoc-arrays/72/

Modelsim AE seems to fail on large Verilog 2000 style memory declarations liek above:

# do modelsim.do# vsim -novopt -L work test # Start time: 09:33:47 on Apr 06,2016# // ModelSim ALTERA 10.4b May 27 2015 Linux 2.6.32-504.23.4.el6.x86_64# //# // Copyright 1991-2015 Mentor Graphics Corporation# // All Rights Reserved.# //# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.# //# Loading work.test# ** Fatal: (vsim-4) ****** Memory allocation failure. *****# Attempting to allocate 16777240 bytes# Please check your system for available memory and swap space.# ** Fatal: (vsim-4) ****** Memory allocation failure. *****# Attempting to allocate 16777224 bytes# Please check your system for available memory and swap space.# ** Warning: (vsim-3116) Problem reading symbols from /home/tools/altera/15.1/modelsim_ae/linuxaloem/vsimk : can not allocate memory for reading ELF file.

Our host has 24G of physical memory and it's mostly free (20G) when we run the sim. So I don't think the error message is very accurate.

This is annoying.....but we've modified the legacy code and used SV style declarations to fix this.

Regards,

John Pavan

From my understanding, in any simulator, declaring a memory like you did will always require the full area to allocated. Your error message seems to indicate it is struggling to allocate 16mb, which may indicate a system problem?

The memory you describe is not very large and shouldnt require much system memory.

A sparse memory would have to be simulated with something like an associative array as you suggest, but this is not synthesisable. This would mean you would swap out your synthesisable code with your sparse memory model. But for such a small ram, I would never use such a thing as it is so small (when you start talking about DDRs, then you should think about sparse modelling).

We know for a fact that VCS and NCverilog support sparse memories and do not require the full memory to be allocated. We've used this capability many times. Older Modelsim docs discuss this capability too.

We don't have a system problem. We have plenty of physical and virtual memory.

We agree that sparse memories are not synthesizable and that SV associative arrays are not synthesizable. Our need is in test bench code so SV associative arrays are acceptable.

The manuals which came with older versions of ModelSim had more discussion. Based on some of that information here's one way to try to control if a memory is sparse:

reg /*sparse*/  mem0;

But then the tools warn that they won't support it:

vlog test.v 
Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
-- Compiling module test
** Warning: test.v(4): (vlog-2154) Cannot mark any array in personal edition as sparse.

It seems like SparseMemThreshold in modelsim.ini is ignored as well.

It seems strange that the tools would intentionally ignore attempts to implement plain old arrays as sparse, but then support SystemVerilog associative arrays.

The clue is in the warning:

** Warning: test.v(4): (vlog-2154) Cannot mark any array in personal edition as sparse.

So you need a more expensive version of modelsim to use it. PE (Personal/Pauper's edition) is one of the cheapest licences.

You forget that the sparse memories you are talking about are controlled by the tool, and allow large memories in code to be run and use less memory without any input from the user. Allowing you to run a large design without running out of ram (if you paid enough money).

Assosiative arrays are controlled by the user and therefore out of the tools hands.

--- Quote Start ---

The clue is in the warning:

You forget that the sparse memories you are talking about are controlled by the tool

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As I mentioned the older manuals give users several options for controlling when sparse memories are used for Verilog arrays. (meta comments, mti, .ini files) Much discussion has been removed from the more recent manuals though.

There doesn't seem to be a chart detailing which tools support this. I imagine that most people just use SystemVerilog for such modelling now and don't look back. It's pretty easy to make these edits to legacy models, so I don't see why anyone would pay extra for it. So it's strange that this is an extra cost feature. Whereas other much more involved features such as mixed language support are now available in PE out of the box.