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The clue is in the warning:
You forget that the sparse memories you are talking about are controlled by the tool
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As I mentioned the older manuals give users several options for controlling when sparse memories are used for Verilog arrays. (meta comments, mti, .ini files) Much discussion has been removed from the more recent manuals though.
There doesn't seem to be a chart detailing which tools support this. I imagine that most people just use SystemVerilog for such modelling now and don't look back. It's pretty easy to make these edits to legacy models, so I don't see why anyone would pay extra for it. So it's strange that this is an extra cost feature. Whereas other much more involved features such as mixed language support are now available in PE out of the box.
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