Does modelsim_ae 15.1 support sparse memories?

We know for a fact that VCS and NCverilog support sparse memories and do not require the full memory to be allocated. We've used this capability many times. Older Modelsim docs discuss this capability too.

We don't have a system problem. We have plenty of physical and virtual memory.

We agree that sparse memories are not synthesizable and that SV associative arrays are not synthesizable. Our need is in test bench code so SV associative arrays are acceptable.