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You will need to register your input to ensure your design does not have issues. If your design permits, I recommend registering all inbound signals before using them in your logic.
To pass the clock-wide pulse to a slower domain is not horrible, it just takes some logic to work. I am not great at verilog, so I'm posting a VHDL clock sync design. It isn't the greatest, but you should be able to get an idea on how it can work. It has restrictions on maximum pulse rate on fast clock domain vs fast/slow clock speed ratio. *Disclaimer: I did not try to compile this so errors may exist.
PROCESS(FAST_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
input_register_s <= '0';
feedback_register_s <= '0';
ELSIF (rising_edge(FAST_CLK)) THEN
input_register_s <= SigA; //register the input
feedback_register_s <= slow_domain_status_register_s; //register the feedback from slow domain
IF (input_register_s = '1') THEN //if pulse detected, set feedforward
feedforward_register_s <= '1';
ELSIF (feedback_register_s = '1') THEN //if feedback indicates pulse seen at slow domain clear feedforward
feedforward_register_s <= '0';
END IF;
END IF;
END PROCESS;
PROCESS(SLOW_CLK, RESET)
BEGIN
IF (RESET = '1') THEN
slow_domain_status_register_s <= '0';
slow_domain_status_register1_s <= '0';
slow_domain_SigA <= '0';
ELSIF (rising_edge(SLOW_CLK)) THEN
slow_domain_status_register_s <= input_register_s; //register on new clock domain
slow_domain_status_register1_s <= slow_domain_status_register_s; //remember what last value was
IF ((slow_domain_status_register1_s = '0') AND (slow_domain_status_register_s = '1')) THEN //rising edge detect
slow_domain_SigA <= '1'; //send pulse in slow domain
ELSE
slow_domain_SigA <= '0';
END IF;
END IF;
END PROCESS;
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Thanks for getting back to me. Can we not just set input_register_s to 1 upon SigA assertion? Then pass the Input_register_s to slow clock domain - synchronize it and generate single pulse using AND gate. Doing so will ensure that it works in any clock domain fast to slow or slow to fast. This method does not require feedback as there is only one SigA pulse. Also as per my understanding, it takes two flipflop to synchronize the asynchronous signal. Just curious. Sorry here is what I was thinking in verilog.
//Synchronize the input signal as it is going through AND gate
//Also not clear on the external trace length mis-match
//between AClk and SigA
always @(posedge AClk or posedge Reset) begin
if (Reset) begin
SigAQ0 <= 1'b0;
SigAQ1 <= 1'b0;
end
else begin
SigAQ0 <= SigA;
SigAQ1 <= SigAQ0;
end
end
//Generate SigAFlag based on SigAQ1 pulse
//SigAFlag asserts upon SigA assertion
always @(posedge AClk or posedge Reset) begin
if (Reset) begin
SigAFlag <= 1'b0;
end
else begin
if (SigAQ1) begin
SigAFlag <= 1'b1;
end
else begin
SigAFlag <= SigAFlag;
end
end
end
//Synchronize the SigAFlag to BClk domain and generate SigB
always @(posedge BClk or posedge Reset) begin
if (Reset) begin
SigBQ0 <= 1'b0;
SigBQ1 <= 1'b0;
SigBQ2 <= 1'b0;
SigB <= 1'b0;
end
else begin
SigBQ0 <= SigAFlag;
SigBQ1 <= SigBQ0;
SigBQ2 <= SigBQ1;
SigB <= SigBQ1 & ~SigBQ2;
end
end
It will be great if you can provide feedback.
Honored Contributor
