Do I need synchronizer block for this

You will need to register your input to ensure your design does not have issues. If your design permits, I recommend registering all inbound signals before using them in your logic.

To pass the clock-wide pulse to a slower domain is not horrible, it just takes some logic to work. I am not great at verilog, so I'm posting a VHDL clock sync design. It isn't the greatest, but you should be able to get an idea on how it can work. It has restrictions on maximum pulse rate on fast clock domain vs fast/slow clock speed ratio. *Disclaimer: I did not try to compile this so errors may exist.

PROCESS(FAST_CLK,RESET)
BEGIN
  IF(RESET = '1') THEN
    input_register_s <= '0';
    feedback_register_s <= '0';
  ELSIF (rising_edge(FAST_CLK)) THEN
    input_register_s <= SigA;  //register the input
    feedback_register_s <= slow_domain_status_register_s;  //register the feedback from slow domain
    IF (input_register_s = '1') THEN //if pulse detected, set feedforward
      feedforward_register_s <= '1';
    ELSIF (feedback_register_s = '1') THEN  //if feedback indicates pulse seen at slow domain clear feedforward
      feedforward_register_s <= '0';
    END IF;
  END IF;
END PROCESS;
PROCESS(SLOW_CLK, RESET)
BEGIN
  IF (RESET = '1') THEN
    slow_domain_status_register_s <= '0';
    slow_domain_status_register1_s <= '0';
    slow_domain_SigA <= '0';
  ELSIF (rising_edge(SLOW_CLK)) THEN
    slow_domain_status_register_s <= input_register_s;  //register on new clock domain
    slow_domain_status_register1_s <= slow_domain_status_register_s;  //remember what last value was
    IF ((slow_domain_status_register1_s = '0') AND (slow_domain_status_register_s = '1')) THEN  //rising edge detect
      slow_domain_SigA <= '1';  //send pulse in slow domain
    ELSE
      slow_domain_SigA <= '0';
    END IF;
  END IF;
END PROCESS;