Do I need synchronizer block for this

Thanks for response. I am bit concerned about the way I have used the AND gate to derive single pulse as in following statement

SigB <= SigBQ1 & ~SigBQ2;

Normally I see people using XOR gate. I do not know why to use XOR instead of AND.

I see the following paper from Cadence suggesting some issue with AND gate but they did not provide a solution. In the figure CLKA and CLKB to be same clock frequency.

http://w2.cadence.com/whitepapers/cdc_wp.pdf Section 3.3 figure 6.

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The reason for the feedback is to clear the flag in the fast clock domain to look for more pulses. If you will only have one ever between resets, your code should work fine. If you have multiple pulses, you need a way to clear SigAFlag in your fast domain.

I have seen recommendations to use two registers to cross clock domains. Although it may be bad practice, I have always used one and had no real issues with it. Using two shouldn't be a problem, it will just take a little more time and a few more resources. Good luck with your design!

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