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Altera_Forum
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13 years ago

Do I need synchronizer block for this

i am feeding reset, aclk and siga to the fpga as input. aclk is running very fast may be 350mhz. siga is one aclk period wide and derived from synchronizer block and then anded to gather before goi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

If a straight XOR is used, you will get two pulses, one for the rising edge, and one for the falling edge. Your use of the & operator should not be a problem. Both SigBQ1 and SigBQ2 are not crossing domains as shown in your document's figure 6.