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Altera_Forum's avatar
Altera_Forum
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13 years ago

Do I need synchronizer block for this

i am feeding reset, aclk and siga to the fpga as input. aclk is running very fast may be 350mhz. siga is one aclk period wide and derived from synchronizer block and then anded to gather before goi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

SigBQ1 is going high and staying high and then one clock later SigBQ2 is doing the same thing. so AND or XOR gate should generate the same result of one BClk wide pulse.