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wenna's avatar
wenna
Icon for New Contributor rankNew Contributor
1 year ago

Direct operations on strings will result in synthesis errors.

Consider the following code, which fails synthesis.

module test1 (y, clk);
  output wire y;
  input wire clk; 
  wire wire1; 
  assign wire1 = $signed((~""));
  assign y = wire1;
endmodule

However, when I use a register to store the value before performing operations, it synthesizes successfully.

module test1 (y, clk);
  output wire y;
  input wire clk; 

  wire wire1; 
  reg str = "";
  assign wire1 = $signed(~str);
  assign y = wire1;
endmodule
Hdl

3 Replies

  • _AK6DN_'s avatar
    _AK6DN_
    Icon for Frequent Contributor rankFrequent Contributor
    1 year ago

    The compiler is right, you are wrong.

    I'm not even sure what you expect $signed((~"")) to return as a value. It is nonsensical.

    You are doing logical bitwise negation on an empty string value. What do YOU expect that to return?

    reg str = "";
wire wire1 = $signed(~str);

    The first line is valid as it defines a one bit register named str that gets an initial value of "" (whatever that is, probably 1'0b but that is a guess).

    The second line is valid as it returns the $signed() of the bitwise complement of a one bit register.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    The "" in the failing code represents an empty string, which is not a standard numeric literal in Verilog. The bitwise NOT operator ~ applied to a non-numeric type (empty string) is not well-defined and can lead to synthesis issues.

    In line:

    reg str = "";

    The reg type expects a single-bit value, and "" is treated as an implicit zero or 1'b0 as mentioned by @_AK6DN_

    Regards,

    Richard Tan

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

    If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

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    Best Regards,

    Richard Tan