Forum Discussion
wenna
New Contributor
New ContributorDirect operations on strings will result in synthesis errors.
Consider the following code, which fails synthesis. module test1 (y, clk);
output wire y;
input wire clk;
wire wire1;
assign wire1 = $signed((~""));
assign y = wire1;
endmodule Howe...
RichardT_altera
Super Contributor
Super ContributorThe "" in the failing code represents an empty string, which is not a standard numeric literal in Verilog. The bitwise NOT operator ~ applied to a non-numeric type (empty string) is not well-defined and can lead to synthesis issues.
In line:
reg str = "";
The reg type expects a single-bit value, and "" is treated as an implicit zero or 1'b0 as mentioned by @_AK6DN_
Regards,
Richard Tan
