Different bitstream produced by Quartus II v10.1 - Windows Linux

Hi Daixiwen, thanks for your quick reply.

Is it documented somewhere what you reported ?

My problem is that while the Linux version seems to work correctly in real HW, that's not the case for the Windows version.

i can confirm what Daixiwen says, i don't know if it's in any documentation

i suspect constraints issues if the two builds aren't working the same

Hi thepancake,

I am afraid you're right. Today I continued to work on my linux project.

First compilation: it works.

Second compilation (added Signaltap): it works.

Third compilation (increased buffer in Signaltap): it DOES NOT work.

Fourth compilation (decreased buffer in Signaltap, but increased respect to Second compilation): it works.

Actually I do not meet timing requirements. The fastest internal clock is 150MHz (generated by an internal PLL from a 125MHz external clock) in an Arria II GX.

I used Synopsys Synphony for most of the project (I tried to follow the timing guidelines found in its documentation, e.g. "fixed latency = 1"), but probably it was not enough.

Hi,

I found on Altera documentation that passing from Windows to Linux the bitstream may vary.

From "Quartus II Handbook Version 11.1 Volume 2: Design Implementation and Optimization":

Any design change that directly or indirectly affects the Fitter has the same type of random effect as changing the seed value. This includes any change in source files, Analysis & Synthesis Settings, Fitter Settings, or Timing Analyzer Settings. The same effect can appear if you use a different computer processor type or different operating system, because different systems can change the way floating point numbers are calculated in the Fitter.

Now I really have to carefully analyse my design in order to eliminate timing violations that probably are causing my problems.

Did anybody have timing problems with a model created with Synopsys Synphony?

You should check that your timing constraints are correct. First check the frequency of your clock sources and generated clocks (you can use the report clocks function in Timequest and compare the frequencies with the real ones).

Then check that all your false paths are real false paths, to be sure that Timequest doesn't forget to analyse some paths.

Then check that all your I/O pins are constrained (there is a report for unconstrained ports), and that their constraints are correct.

Hi Daixiwen,

my Quartus design is composed mostly by a block generated with Synopsys Synphony.

The timing violations I get in timequest (slack of -6ns) for many many signals are related to the Synphony generated block.

I feed the Synphony generated block with a 150MHz clock produced by a FPGA PLL and then inside it I use this clock to generate other 3 slower frequencies.

Synopsys Synphony generates the following timing constraints:

define_clock -name {n:clkDiv1875} -freq 0.080000 -clockgroup default_dsp_clkgroup

define_clock -name {n:clk} -freq 150.000000 -clockgroup default_dsp_clkgroup

define_clock -name {n:clkDiv15} -freq 10.000000 -clockgroup default_dsp_clkgroup

define_clock -name {n:clkDiv5} -freq 30.000000 -clockgroup default_dsp_clkgroup

define_input_delay -disable {tx_fifo_empty} 0 -ref clk:r

define_input_delay -disable {tx_fifo_Q_data[15:0]} 0 -ref clk:r

define_input_delay -disable {tx_fifo_I_data[15:0]} 0 -ref clk:r

define_input_delay -disable {fifo_control_empty} 0 -ref clk:r

define_input_delay -disable {fifo_control_data[49:0]} 0 -ref clk:r

define_input_delay -disable {Data_from_ADC[13:0]} 0 -ref clk:r

define_output_delay -disable {tx_fifo_rdreq} 0 -ref clk:r

define_output_delay -disable {rx_fifo_strobe} 0 -ref clk:r

define_output_delay -disable {rx_fifo_q_data[15:0]} 0 -ref clk:r

define_output_delay -disable {rx_fifo_i_data[15:0]} 0 -ref clk:r

define_output_delay -disable {fifo_control_rdreq} 0 -ref clk:r

define_output_delay -disable {debug[13:0]} 0 -ref clkDiv1875:r

define_output_delay -disable {Data_to_DAC[13:0]} 0 -ref clk:r# Do not pack registers in IO pads# This will be relevant if designer inserts IO

define_global_attribute syn_useioff {0}

define_multicycle_path -through {n:ti_sincgars_wrapper_model_Tx.DDC_WF_block.myDDC_WF.DDC_WF_filter_Q_block.myDDC_WF_filter_Q.CIC_DDC_block.myCIC_DDC.N_6[0:36]} -start 124

define_multicycle_path -through {n:ti_sincgars_wrapper_model_Tx.DDC_WF_block.myDDC_WF.DDC_WF_filter_I_block.myDDC_WF_filter_I.CIC_DDC_block.myCIC_DDC.N_6[0:36]} -start 124

define_multicycle_path -through {n:ti_sincgars_wrapper_model_Tx.Freq_translation_and_DDC_Platform_block.myFreq_translation_and_DDC_Platform.DDC_filter_I_block.myDDC_filter_I.FIR_Rate_Converter_DDC_block.myFIR_Rate_Converter_DDC.N_Downsample_RG3_1_294[0:15]} -start 2

define_multicycle_path -through {n:ti_sincgars_wrapper_model_Tx.Freq_translation_and_DDC_Platform_block.myFreq_translation_and_DDC_Platform.DDC_filter_I_block.myDDC_filter_I.CIC_DDC_block.myCIC_DDC.N_6[0:22]} -start 4

define_multicycle_path -through {n:ti_sincgars_wrapper_model_Tx.Freq_translation_and_DDC_Platform_block.myFreq_translation_and_DDC_Platform.DDC_filter_Q_block.myDDC_filter_Q.FIR_Rate_Converter_DDC_block.myFIR_Rate_Converter_DDC.N_Downsample_RG0_1_287[0:15]} -start 2

define_multicycle_path -through {n:ti_sincgars_wrapper_model_Tx.Freq_translation_and_DDC_Platform_block.myFreq_translation_and_DDC_Platform.DDC_filter_Q_block.myDDC_filter_Q.CIC_DDC_block.myCIC_DDC.N_6[0:22]} -start 4

that are different from how Quartus want them. Maybe there is a difference between a SDC file for synopsys and a SDC for quartus.

Anyway the 3 slower frequencies are not listed in the clock list, I have somehow to constrain them in quartus.

how do you generate these 3 slower frequencies? do you use a PLL? or are you generating them in logic?

With logic generated clocks, you are liable to get setup and hold time violations. It is much better to generate clock enables in the system clock domain.

Hi Tricky,

these 3 frequencies are generated automatically by Synopsys Synphony. It is not used a PLL, but with logic and enable signals.

Now the situation is the following one:

- with Synphony I manage to meet the timing constraints (by using retiming and advanced timing). It shouls use Synplify Pro to reach this result.

- when I compile in Quartus I still do not manage to set all timing constraints specified in Synplify Pro format. In particulat I do not manage to find the node to which the define_multicycle_path apply. I used the node finder in timeQuest in order to do that.

Anyone knows how to pass from Synplify Pro SDC constraints to Quartus SDC constraints ?

Thanks

Bye