Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi thepancake,
I am afraid you're right. Today I continued to work on my linux project. First compilation: it works. Second compilation (added Signaltap): it works. Third compilation (increased buffer in Signaltap): it DOES NOT work. Fourth compilation (decreased buffer in Signaltap, but increased respect to Second compilation): it works. Actually I do not meet timing requirements. The fastest internal clock is 150MHz (generated by an internal PLL from a 125MHz external clock) in an Arria II GX. I used Synopsys Synphony for most of the project (I tried to follow the timing guidelines found in its documentation, e.g. "fixed latency = 1"), but probably it was not enough.