Forum Discussion
Occasional ContributorDesign Example for LVDS rx in MAX10
Hi.
I am working on max10 project where i want to receive serial data coming at data rate of 480Mbps, and need to convert it into parallel data for the i used Altera soft lvds ip core, my problem sometimes data was not aligned and sometime it was getting correctly.
I need to convert serial data into 12 bit parallel data.
IP configuration:
Mode = rx,
No of channels = 4,
SERDES factor = 7,
data rate = 480 Mbps,
Input clock = 240 MHz,
phase shift = 0 degree.
For data realignment i need to use bit slip function, i am not getting how to generate rx channel data align pulse can i get an example code for to generate rx_channel _data_allign pulse.
4 Replies
AminT_IntelRegular Contributor
Hello,
Do you know why your data is not aligned sometimes?
Here's some videos on LVDS IP that you can refer to:
1. https://www.youtube.com/watch?v=02lgfcxSjQA
2. https://www.youtube.com/watch?v=EAJ4BIiH-6I
Thank you,
Amin
m_kumarHi ,
Initially i want to detect an 12'hE9C idle pattern for some clock cycles (ex: 282 clocks), output of lvds rx ip output is 6 bit and i am using shift register to convert 6 bit to 12 bit.
required output E9C = 111010011100 .
sometimes i receive: 110100111001, 100111010011, like that for every power on bit position was changing from one position to other position.
Now i need to write bit slip logic using state machine or in Quartus has any built solution for this.
Regards
manoj
- AminT_Intel
Hello Manoj,
You can refer to Data Realignment Block (Bit Slip) in this document on page 27: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf
Thank you
