Design Example for LVDS rx in MAX10

Hi.

I am working on max10 project where i want to receive serial data coming at data rate of 480Mbps, and need to convert it into parallel data for the i used Altera soft lvds ip core, my problem sometimes data was not aligned and sometime it was getting correctly.

I need to convert serial data into 12 bit parallel data.

IP configuration:

Mode = rx,

No of channels = 4,

SERDES factor = 7,

data rate = 480 Mbps,

Input clock = 240 MHz,

phase shift = 0 degree.

For data realignment i need to use bit slip function, i am not getting how to generate rx channel data align pulse can i get an example code for to generate rx_channel _data_allign pulse.