Occasional Contributor
Regular ContributorHello,
Do you know why your data is not aligned sometimes?
Here's some videos on LVDS IP that you can refer to:
1. https://www.youtube.com/watch?v=02lgfcxSjQA
2. https://www.youtube.com/watch?v=EAJ4BIiH-6I
Thank you,
Amin
Occasional ContributorHi ,
Initially i want to detect an 12'hE9C idle pattern for some clock cycles (ex: 282 clocks), output of lvds rx ip output is 6 bit and i am using shift register to convert 6 bit to 12 bit.
required output E9C = 111010011100 .
sometimes i receive: 110100111001, 100111010011, like that for every power on bit position was changing from one position to other position.
Now i need to write bit slip logic using state machine or in Quartus has any built solution for this.
Regards
manoj
