Design compilation not possible with newer version of Quartus Prime

The error message indicate that ::

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the read logic for the RAM is not fully synchronous.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, ensure that either the read address or the output of the RAM are registered.

You may also checkout the KDB below:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086642.html

• The read address is registered but has a preserve attribute attached to it.
• The read address is registered but has a fast_input_register assignment and is implemented as an IO register.

Above scenarios will also cause the RAM to be uninferred.

Regards,

Richard Tan