Altera_Forum
Honored Contributor
17 years agoDesign Being Removed
Hi,
When I synthesize my design solely, the report is fine. But when I put it in an SOPC built design, only the top module which has only two pins (clock and a key) is left after synthesis. To be exact, report says number of logic elements used is "zero"! Does this mean because the design has no output in terms of pins, is being removed?! So how come I don't see any warning or info messages about it?! I'd really appreciate any help. Thanks, Kaveh