Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Design Being Removed

Hi, When I synthesize my design solely, the report is fine. But when I put it in an SOPC built design, only the top module which has only two pins (clock and a key) is left after synthesis. To ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

If you don't have any output ports, then the design gets synthesized away. (How would the design do anything if it never tells anyone what it's doing)? That beings said, you should get a lot of messages in analysis and synthesis about registers being removed. The only thing I can think is you may be suppressing this messages(alond the messages tabs there is one for suppressed messages.) I've seen tons of logic get removed, but I always see messages about it. (The generat complaint is that there are to many messages, hence the suppression manager).