Design assistant upgrade behavior

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I have upgraded my development environment from quartus ii 32bit 12.0sp2 build 263 web edition to quartus ii 32bit 13.1.0 build 162 web edition.

Now the same project on the newest environment reports rule violations that were never reported by the old environment, that are:

R104, D101, D103, R105, D102.

As I have a backup of old environment I have made some check between old and new environment, especially I have checked that nothing is changed in the project.

But result is always same, the above violations are reported.

Of course such project is in production since several years, and I never got consistency problem.

Any idea?

Thanks in advance.

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It should be easy to double check the rules yourself.

you can check if the messages are grouped under suppressed category in the case they don't show.

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It should be easy to double check the rules yourself.

you can check if the messages are grouped under suppressed category in the case they don't show.

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Yes, I could do that.

But before beginning a potentially time-expensive activity, I would like to understand the main topic, that is: why up to version 12.0sp2 everything was fine and now the 13.1 raise all such issues?

My actions was just upgrade development environment to 13.1, then open the project and build.

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Yes, I could do that.

But before beginning a potentially time-expensive activity, I would like to understand the main topic, that is: why up to version 12.0sp2 everything was fine and now the 13.1 raise all such issues?

My actions was just upgrade development environment to 13.1, then open the project and build.

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You don't need to do any major work. Just check one single case to see which tool is not telling the truth. I expect the one that tells you is right and the one that didn't was not efficient enough.

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You don't need to do any major work. Just check one single case to see which tool is not telling the truth. I expect the one that tells you is right and the one that didn't was not efficient enough.

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I did it for some of such issues: it seems in all cases related to data transfer between two different clock domains, both generated by the same PLL, 160MHz and 40MHz.

Aren't the two generated by same PLL synchronous?

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I did it for some of such issues: it seems in all cases related to data transfer between two different clock domains, both generated by the same PLL, 160MHz and 40MHz.

Aren't the two generated by same PLL synchronous?

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I'm have the same issue with D101 and D103 messages about signals passing from synchronous integer multiple clock speed domains i.e. 60MHz to 120MHz.

I've included the clocks in the same clock group and I'm getting no timing errors between the clock domains.

Can I ignore the warnings or is there something that can be done to help the tool understand the architecture?

Any help would be appreciated.