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I did it for some of such issues: it seems in all cases related to data transfer between two different clock domains, both generated by the same PLL, 160MHz and 40MHz.
Aren't the two generated by same PLL synchronous?
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I'm have the same issue with D101 and D103 messages about signals passing from synchronous integer multiple clock speed domains i.e. 60MHz to 120MHz.
I've included the clocks in the same clock group and I'm getting no timing errors between the clock domains.
Can I ignore the warnings or is there something that can be done to help the tool understand the architecture?
Any help would be appreciated.
Honored Contributor
