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Altera_Forum's avatar
Altera_Forum
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12 years ago

DE2-115 DDR2 Controller

Hi everyone!

I'm currently working on an implementation that requires me to store packets into the SDRAM then fetch it when it is optimal to transmit. I am having trouble on making it work though.

The way I understand it, I have two options.

  1. Use NIOS through QSYS then access the memory using C programming.

  2. Use AVALON INTERFACE and MegaWizard to generate the necessary IP.

What I have done so far:

for the nios:

Introduction to the Altera Qsys System Integration Tool

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/introduction_to_the_altera_qsys_tool.pdf -- use this until the part of compilation. stop in the step where altera monitor is being discussed. it is already outdated and is replaced by a built in eclipse.

Using the SDRAM on Altera’s DE2-115 Board with VHDL Designs

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/vhdl/de2-115/using_the_sdram.pdf -- this completes the whole nios system with sdram. problem at this point is how to access the sdram now that it has a controller. tutorial did not give any insights about doing this

i want to extract the data from the memory to a logic outside the nios system. in essence, i am just using the nios to access the memory because this is the easier tutorial that i have found online. however, it lacks the succeeding steps.

for the avalon:

AVALON MEMORY MAP INTERFACE

Chapter 3. Avalon Memory-Mapped Interfaces

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

Embedded Peripherals IP USER GUIDE

Chapter 2. SDRAM Controller Core

http://www.altera.com/literature/ug/ug_embedded_ip.pdf

External Memory Interface Handbook - Volume 2: Design Guidelines

Chapter 9. Implementing and Parameterizing Memory IP

http://www.altera.com/literature/hb/external-memory/emi_plan.pdf

From this, I have deduced that the SDRAM controls will be handled by the IP built by Altera, and the only thing that I should have problem is utilizing the Avalon-MM Slave Port. This might be a good idea for developers who are already familiar with altera because the Avalon interface is used in many IP but since this is my first time to use such interface, I am lost on how to proceed.

i know that this is a more straight forward approach but i can't find the right timing diagram to create an fsm that will utilize the signals. moreover, i need more information on each control and data signals. on top of that, during the creation of the ip with megawizard, i don't have any idea on what to put into the parameters of the sdram because the de2-115 did not specify what chip it is.

Here are the information that I know about the SDRAM in DE2-115.

  • DDR2 - 128MB

  • 16 data lines shared for both SDRAM making it access 32 bit of data per address locations.

  • It has 13 address lines and 2 address lines for the banks.

  • Address Banks = (2^13) (2^10) (2^2) = 8192 1024 * 4 = 33554432 address locations = 32M

  • 32M words x 32 bits/word = 1028 Mbits = 128MB

I'm glad to have any help from either approach. I've been stuck here for almost two weeks. I tried my best to gather all the information that I can but it is not enough. I hope someone can enlighten me about DDR2 addressing.

Many thanks!

17 Replies

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  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I also have the SDRAM Controller but I don't know which one of the following Avalon to use or am I looking in the right place?

    • Avalon-MM Clock Crossing Bridge

    • Avalon-MM DDR Memory Half Rate Bridge

    • Avalon-MM Pipeline Bridge

    • Avalon-MM Tristate Bridge

    • JTAG to Avalon Master Bridge

    • SPI Slave to Avalon Master Bridge

    --- Quote Start ---

    I clearly see in my QSYS a component called "SDRAM Controller". You have 2 options: export Avalon MM interface from QSYS to Quartus or add your custom peripheral to QSYS.

    --- Quote End ---

    I don't understand what you mean by export "Avalon MM interface from QSYS to Quartus" The way I understand QSYS is that you need to build the whole system before you can successfully export the modules. Or do you mean I have to import Avalon MM interface from somewhere?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Look for "Click to export" in Qsys. So you can make the whole Avalon MM slave interface available in Quartus.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Look for "Click to export" in Qsys. So you can make the whole Avalon MM slave interface available in Quartus.

    --- Quote End ---

    You mean this set of codes will appear? That did remove the error "must be connected to an avalon-MM master." I can export this now. 

    
        .sdram_0_s1_address       (<connected-to-sdram_0_s1_address>),       // sdram_0_s1.address
        .sdram_0_s1_byteenable_n  (<connected-to-sdram_0_s1_byteenable_n>),  //           .byteenable_n
        .sdram_0_s1_chipselect    (<connected-to-sdram_0_s1_chipselect>),    //           .chipselect
        .sdram_0_s1_writedata     (<connected-to-sdram_0_s1_writedata>),     //           .writedata
        .sdram_0_s1_read_n        (<connected-to-sdram_0_s1_read_n>),        //           .read_n
        .sdram_0_s1_write_n       (<connected-to-sdram_0_s1_write_n>),       //           .write_n
        .sdram_0_s1_readdata      (<connected-to-sdram_0_s1_readdata>),      //           .readdata
        .sdram_0_s1_readdatavalid (<connected-to-sdram_0_s1_readdatavalid>), //           .readdatavalid
        .sdram_0_s1_waitrequest   (<connected-to-sdram_0_s1_waitrequest>)    //           .waitrequest

    From here, I can just work on the logic using the avalon interface guide right? Thank you for sharing your knowledge on this. I have a simple request though. I have read that guide but do you know any straight forward guide that could help me develop my design? An example will be of great help to me :)
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I am not sure at this point if I need to add a PLL for the SDRAM. With the NIOS implementation, the PLL was crucial.

    --- Quote Start ---

    The clock skew depends on physical characteristics of the DE2-115 board. For proper operation of the SDRAM chip,

    it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds.

    This can be accomplished by using a phase-locked loop (PLL) circuit which can be manually created using the MegaWizard plug-in. It can also be created automatically using the Clock Signals IP core provided by the Altera

    University Program. We will use the latter method in this tutorial.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    address, writedata, readdata, readdatavalid, read_n and write_n are self explaining singals. byteenable_n can be constant '0'. chipselect can be tied to '1' if only your peripheral has access to that SDRAM. slave asserts waitrequest when it is busy.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    address, writedata, readdata, readdatavalid, read_n and write_n are self explaining singals. byteenable_n can be constant '0'. chipselect can be tied to '1' if only your peripheral has access to that SDRAM. slave asserts waitrequest when it is busy.

    --- Quote End --- 

    wire  sdram_avl_address;       // sdram_avl.address
wire   sdram_avl_byteenable_n;  //          .byteenable_n
wire        sdram_avl_chipselect;    //          .chipselect
wire  sdram_avl_writedata;     //          .writedata
wire        sdram_avl_read_n;        //          .read_n
wire        sdram_avl_write_n;       //          .write_n
wire  sdram_avl_readdata;      //          .readdata
wire        sdram_avl_readdatavalid; //          .readdatavalid
wire        sdram_avl_waitrequest;   //          .waitrequest
wire        reset_reset_n;           //     reset.reset_n

    Looking at the instantiated code, I think you were right when you said that it is straightforward. I started with DDR2 IP Core which has complicated address signals. The way I see it, the addressing concatenated the rows, columns, and bank which has 13, 10, and 2 bits respectively to create an address signal of 25 bits. Moreover, the write and read data has the same word length as the one in the SDRAM. I'll work this thing out.

    Many thanks for your insights sir Linas.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi smdumla!

    you had any progress in your code.

    I'm trying to do the same thing, but I'm finding some inconsistencies!